Not your neighbour's FPU
Version 1.15.2 is out since 23/10/2009!
Check out its release notes and the list of operators, and get it from the InriaGForge page of the project.
FloPoCo is a generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs.
The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm, with a focus on floating-point.
The philosophy of FloPoCo is that floating-point on FPGAs should not rely on operators that mimick those available in processors. By designing radically new operators, one may obtain more accurate results with less hardware in less time. This thesis is detailed in this document.
Therefore FloPoCo focuses on exotic operators and exotic precisions. However it also provides basic operators (+,-,*,/ and square root) whose performance matches vendor-supplied operators while offering more flexibility.
FloPoCo is not a library of operators, but a generator of operators written in C++. It inputs operator specifications, and outputs synthesizable VHDL. This approach allows much better optimization and customization than what VHDL alone permits. In addition, FloPoCo is to our knowledge the easiest way to design complex operators with flexible pipeline.
FloPoCo supersedes FPLibrary, and is compatible with it.
FloPoCo is distributed under the GNU Lesser General Public License (see COPYING.LIB for details). Contributions are welcome!
The operators generated by FloPoCo can be used under the terms of the GNU Lesser General Public License with a Tobin Tax restriction (see README for details). You are free to use and distribute them without changing this license. You are also free to modify them, as long as you make the modifications available. In the latter case please consider modifying FloPoCo instead, or get in touch with the FloPoCo team for this purpose.
Get the latest version from the InriaGForge page of the project
Alternatively, get a development version from the subversion repository.
| [22] | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Racines carrées multiplicatives sur FPGA. In SYMPosium en Architectures nouvelles de machines (SYMPA), Toulouse, September 2009. [ bib | .pdf ] |
| [21] | Florent de Dinechin, Cristian Klein, and Bogdan Pasca. Generating high-performance custom floating-point pipelines. In Field Programmable Logic and Applications. IEEE, August 2009. [ bib | .pdf ] |
| [20] | Florent de Dinechin and Bogdan Pasca. Large multipliers with fewer DSP blocks. In Field Programmable Logic and Applications. IEEE, August 2009. [ bib | .pdf ] |
| [19] | Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, and Florent de Dinechin. FPGA-based computation of the inductance of coils used for the magnetic stimulation of the nervous system. In Biomedical Electronics and Devices, volume 1, pages 151-155, 2008. [.pdf ] |
| [18] | Jérémie Detrey and Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques, 27(6):673-698, 2008. |
| [17] | Christoph Lauter and Florent de Dinechin. Optimising polynomials for floating-point implementation. In Real Numbers and Computers, pages 7-16, 2008. [.pdf ] |
| [16] | Nicolas Brisebarre, Florent de Dinechin, and Jean-Michel Muller. Integer and floating-point constant multipliers for FPGAs. In Application-specific Systems, Architectures and Processors, pages 239-244. IEEE, 2008. [.pdf ] |
| [15] | Florent de Dinechin, Bogdan Pasca, Octavian Cret, and Radu Tudoran. An FPGA-specific approach to floating-point accumulation and sum-of-products. In Field-Programmable Technologies, pages 33-40. IEEE, 2008. [.pdf ] |
| [14] | Jérémie Detrey and Florent de Dinechin. A tool for unbiased comparison between logarithmic and floating-point arithmetic. Journal of VLSI Signal Processing, 49(1):161-175, 2007. [ .pdf ] |
| [13] | Jérémie Detrey, Florent de Dinechin, and Xavier Pujol. Return of the hardware floating-point elementary function. In 18th Symposium on Computer Arithmetic, pages 161-168. IEEE, 2007. [ .pdf ] |
| [12] | Jérémie Detrey and Florent de Dinechin. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, 31(8):537-545, 2007. [ .pdf ] |
| [11] | Florent de Dinechin, Jérémie Detrey, Ionut Trestian, Octavian Cret, and Radu Tudoran. When FPGAs are better at floating-point than microprocessors. Technical Report ensl-00174627, École Normale Supérieure de Lyon, 2007. [ http ] |
| [10] | Jérémie Detrey and Florent de Dinechin. Floating-point trigonometric functions for FPGAs. In Field-Programmable Logic and Applications, pages 29-34. IEEE, 2007. [ .pdf ] |
| [9] | Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques. précision, performance et validation. Mémoire d'habilitation à diriger les recherches, 2007. [ .pdf ] |
| [8] | Sylvain Collange, Jérémie Detrey, and Florent de Dinechin. Floating point or LNS: choosing the right arithmetic on an application basis. In 9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD'2006), pages 197-203, Dubrovnik, Croatia, 2006. IEEE. [ .pdf ] |
| [7] | Jérémie Detrey and Florent de Dinechin. Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et science informatiques, 24(6):625-643, 2005. |
| [6] | Florent de Dinechin and Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, 54(3):319-330, 2005. [ .pdf ] |
| [5] | Jérémie Detrey and Florent de Dinechin. Table-based polynomials for fast hardware function evaluation. In Application-specific Systems, Architectures and Processors, pages 328-333. IEEE, 2005. [ .pdf ] |
| [4] | Jérémie Detrey and Florent de Dinechin. A parameterizable floating-point logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE, 2005. [ .pdf ] |
| [3] | Jérémie Detrey and Florent de Dinechin. A parameterized floating-point exponential function for FPGAs. In Field-Programmable Technology. IEEE, 2005. [ .pdf ] |
| [2] | Jérémie Detrey and Florent de Dinechin. Second order function approximation using a single multiplication on FPGAs. In 14th Intl Conference on Field-Programmable Logic and Applications (LNCS 3203), pages 221-230. Springer, 2004. [ .pdf ] |
| [1] | Jérémie Detrey and Florent de Dinechin. A VHDL library of LNS operators. In 37th Asilomar Conference on Signals, Systems and Computers, 2003. |
FloPoCo is managed by Florent de Dinechin and Bogdan Pasca (contact: Florent.de.Dinechin at ens-lyon.fr). Active developers: Mioara Joldes, Sebastian Banescu, Sylvain Collange, Radu Tudoran. Former developers: Cristian Klein and Xavier Pujol. Much of FloPoCo's operator code is based on FPLibrary and HOTBM code by Jérémie Detrey. The following people have contributed to FloPoCo in some sort or some other: Mariusz Grad, Daniele Mastrandrea.
FloPoCo uses Sollya, developed by Christoph Lauter, Sylvain Chevillard and Mioara Joldes. It also relies on GMP and MPFR.
Special thanks to the GHDL project for providing us a perfectly useable VHDL simulator that we can use when we are away from our ModelSim license servers.
The support of Stone Ridge Technology is gracefully acknowledged. 