1. Alexandru Plesco. Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. PhD thesis, École normale supérieure de Lyon, September 2010.

1. Christophe Alias, Bogdan Pasca, and Alexandru Plesco. FPGA-Specific Synthesis of Loop Nests with Pipelined Computational Cores. Microprocessors and Microsystems - Embedded Hardware Design, 36(8):606-619, 2012.

1. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In Design, Automation & Test in Europe (DATE'13), Grenoble, France, pages 575-580, March 2013.



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), New Orleans, USA, pages 285-286, February 2012. IEEE Computer Society. Note: Short paper.



3. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), Paris, January 2012. Note: PPoPP'12 extended version.



4. Christophe Alias, Bogdan Pasca, and Alexandru Plesco. Automatic Generation of FPGA-Specific Pipelined Accelerators. In 7th International Symposium on Applied Reconfigurable Computing (ARC'11), Belfast, UK, pages 53-66, March 2011. Springer Verlag.



5. Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco. An FPGA Architecture for Solving the Table Maker's Dilemma. In 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'11), Santa Monica, CA, September 2011. IEEE Computer Society.



6. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-Level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool. In 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Rennes, France, pages 329-332, July 2010. IEEE Computer Society.



7. Alexandru Plesco and Tanguy Risset. Coupling Loop Transformations and High-Level Synthesis. In SYMPosium en Architectures nouvelles de machines (SYMPA'08), February 2008.

1. Christophe Alias, Alain Darte, and Alexandru Plesco. Kernel Offloading with Optimized Remote Accesses. Research Report RR-7697, INRIA, July 2011. [WWW]



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis. Research Report RR-7648, INRIA, June 2011. [WWW]



3. Christophe Alias, Bogdan Pasca, and Alexandru Plesco. FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores. Research Report RR-7674, INRIA, July 2011. [WWW]

1. Christophe Alias Alias and Alexandru Plesco. Procédé de synthèse de circuits, dispositif et programme d'ordinateur associés. Patent number FR1453308, April 2014.

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

Les documents contenus dans ces répertoires sont rendus disponibles par les auteurs qui y ont contribué en vue d'assurer la diffusion à temps de travaux savants et techniques sur une base non-commerciale. Les droits de copie et autres droits sont gardés par les auteurs et par les détenteurs du copyright, en dépit du fait qu'ils présentent ici leurs travaux sous forme électronique. Les personnes copiant ces informations doivent adhérer aux termes et contraintes couverts par le copyright de chaque auteur. Ces travaux ne peuvent pas être rendus disponibles ailleurs sans la permission explicite du détenteur du copyright.

This document was translated from BibT_EX by bibtex2html