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Publications of Tanguy Risset
Thesis
  1. T. Risset. Contribution à la compilation de nids de boucles sur silicium. Thèse d'habilitation à diriger des recherches, Université de Rennes 1, October 2000. [WWW]


  2. T. Risset. Parallélisation automatique: du modèle systolique à la compilation de nids de boucles. Thèse de doctorat, ENS-Lyon, February 1994.


Articles in journal or book chapters
  1. Antoine Fraboulet and Tanguy Risset. Master Interface for On-Chip Hardware Accelerator Burst Communications. Journal of VLSI Signal Processing, 2(1):73-85, 2007.


  2. S. Derrien, A. C. Guillou, P. Quinton, T. Risset, and C. Wagner. Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures. In Domain-Specific Embedded Multiprocessors, chapter 7, pages 127-150. Marcel Dekker, 2003.


  3. F. Dupont de Dinechin, M. Manjunathaiah, T. Risset, and M. Spivey. Design of Highly Parallel Architectures with Alpha and Handel. In System Specification and Design Languages (best of FDL'02). Kluwer, 2003.


  4. S. Rajopadhye, T. Risset, and T. Tadonki. Le chemin algébrique sur réseaux linéaires. Technique et science informatiques, 20(5):655-676, 2001. [WWW]


  5. E. Mémin and T. Risset. On the Study of VLSI Derivation for Optical Flow Estimation. International Journal of Pattern Recognition and Artificial Intelligence (IJPRAI), 14(4):441-462, June 2000. [WWW]


  6. E. Mémin and T. Risset. VLSI Design Methodology for Edge-Preserving Image Reconstruction. Real-Time Imaging, 2000. Note: Special issue on Fast Energy Minimization-Based Imaging and Vision Techniques. [WWW]


  7. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, and T. Risset. Derivation of Systolic Algorithms for the Algebraic Path Problem by Recurrence Transformations. Parallel Computing, 26:1429-1445, 2000. [WWW]


  8. T. Gautier, P. Le Guernic, P. Quinton, S. Rajopadhye, T. Risset, and I. Smarandache. Le projet Cairn : vers la conception d'architectures à partir de Signal et Alpha. In Collection technique et scientifique des télécommunications. CNET, 1997.


  9. P. Quinton, S. V. Rajopadhye, and T. Risset. On Manipulating Z-polyhedra using a Canonical Representation. Parallel Processing Letters, 7(2):181-194, June 1997. [WWW]


  10. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. Integration, the VLSI journal, 17(1):33-51, 1994.


  11. M. Dion, T. Risset, and Y. Robert. Ressource-Constrained Scheduling of Partitioned Algorithms on Processor Arrays. Integration the VLSI journal, 20:139-159, 1994. [WWW]


  12. A. Darte, T. Risset, and Y. Robert. Formal Methods for Solving the Algrebraic Path Problem. In L. Svensson F. Catthoor, editor, Application-Driven Architecture Synthesis, chapter 3, pages 47-69. Kluwer Academic Publishers, 1993.


  13. J.F. Collard, P. Feautrier, and T. Risset. Construction of DO Loops from Systems of Affine Constraints. Parallel Processing Letters, 5:421-436, 1993. [WWW]


  14. T. Risset and Y. Robert. Synthesis of Processor Arrays for the Algebraic Path Problem: Unifying Old Results and Deriving New Architectures. Parallel Processing Letters, 1:19-28, 1991.


  15. T. Risset. Implementing Gaussian Elimination on a Matrix-Matrix Multiplication Systolic Array. Parallel Computing, 16:351-359, 1990.


Conference articles
  1. Alexandru Plesco and Tanguy Risset. Coupling Loop Transformations and High-Level Synthesis. In SYMPosium en Architectures nouvelles de machines (SYMPA'08), February 2008.


  2. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. A Generic Multi-Phase On-Chip Traffic Generation Environment. In IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs, Colorado, USA, September 2006.


  3. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Automatic Phase Detection for Stochastic On-Chip Traffic Generation. In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), seoul, South Corea, pages 88 - 93, October 2006. ACM Press.


  4. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. In IEEE International Conference on Application-Specific Systems, Architecture, and Processors (ASAP'05), pages 28-35, 2005. IEEE Computer Society Press.


  5. Antoine Fraboulet and Tanguy Risset. Efficient On-Chip Communications for Data-Flow IPs. In Application-Specific Systems, Architectures, and Processors (ASAP'04), pages 293-303, 2004. IEEE Computer Society Press.


  6. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architecture, Modeling, and Simulation (SAMOS 2004), volume 3133 of LNCS, pages 453-462, July 2004. Springer Verlag.


  7. Antoine Scherrer, Tanguy Risset, and Antoine Fraboulet. Hardware Wrapper Classification and Requirements for On-Chip Interconnects. In Signaux, Circuits et Systèmes 2004, Monastir, Tunisie, pages 31-34, March 2004.


  8. A.-C. Guillou, P. Quinton, and T. Risset. Hardware Synthesis for Multi-Dimensional Time. In IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 2003.


  9. D. Cachera and T. Risset. Advances in Bit Width Selection Methodology. In IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, July 2002. [WWW]


  10. S. Derrien, A. C. Guillou, P. Quinton, T. Risset, and C Wagner. Automatic Synthesis of Efficient Interfaces for Compiled Regular. In International Samos Workshop on Systems, Architectures, Modeling and Simulation (Samos), Samos, Grèce, July 2002. [WWW]


  11. F. Dupont de Dinechin, M. Manjunathaiah, T. Risset, and M. Spivey. Design of Highly Parallel Architectures with Alpha and Handel. In Forum on Specification and Design Languages (FDL 2002), Marseille, September 2002. [WWW]


  12. D. Cachera, P. Quinton, S. Rajopadhye, and T. Risset. Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. In 6th International Workshop on Formal Methods for Parallel Programming: Theory and Applications (FMPPTA), San Francisco, April 2001. [WWW]


  13. A.-C. Guillou, F. Quilleré, P. Quinton, S. Rajopadhye, and T. Risset. Hardware Design Methodology with the Alpha Language. In FDL'01, Lyon, France, September 2001. [WWW]


  14. M Manjunathaiah, G. M. Megson, T. Risset, and S. Rajopadhye. Uniformization of Affine Dependence Programs for Parallel Embedded System Design. In L.M. Ni and M. Valero, editors, International Conference on Parallel Processing, Valencia, Spain, pages 205-213, 2001. [WWW]


  15. P. Quinton and T. Risset. Structured Scheduling of Recurrence Equations: Theory and Practice. In Proc. of the System Architecture MOdelling and Simulation Workshop, Lecture Notes in Computer Science, Samos, Greece, 2001. Springer Verlag. [WWW]


  16. S. Derrien and T. Risset. Interfacing compiled FPGA programs: the MMAlpha approach. In A. Arabnia, editor, PDPTA2000: Second International Workshop on Engineering of Reconfigurable Hardware/Software Objects, June 2000. CSREA Press. [WWW]


  17. A.C. Guillou, P. Quinton, and T. Risset. Automatic Design of VLSI Pipelined LMS Architectures. In 2000 IEEE Canadian Conference on Electrical and Computer Engineering, Trois Rivières, Canada, August 2000. [WWW]


  18. A. Mozipo, D. Massicote, P. Quinton, and T. Risset. A Parallel Architecture for Adaptative Channel Equalization Based On Kalman Filter Using MMAlpha. In 1999 IEEE Canadian Conference on Electrical and Computer Engineering, 1999.


  19. E. Mémin and T. Risset. Full Alternate Jacobi Minimization and VLSI Derivation of Hardware for Motion Estimation. In International Workshop on Parallel Image Processing and Analysis, IWPIPA'99, Madras, India, January 1999. [WWW]


  20. S. Rajopadhye, T. Risset, and C. Tadonki. The Algebraic Path Problem Revisited. In 5th International Euro-Par Conference, Toulouse, France, pages 698-707, August 1999. [WWW]


  21. T. Risset and Y. Saouter. Synthèse de haut niveau d'un co-processeur pour le calcul des bases de Gröbner. In 5ème Symposium en architecture nouvelles de machines (Sympa'5), Rennes, June 1999. [WWW]


  22. S. Balev, P. Quinton, S. V. Rajopadhye, and T. Risset. Linear Programming Models for Scheduling Systems of Affine Recurrence Equations -- a Comparative Study --. In 10th ACM Symposium on Parallel Algorithms and Architectures (SPAA), 1998. [WWW]


  23. A. Mozipo, D. Massicotte, P. Quinton, and T. Risset. Automatic Synthesis of a Parallel Architecture for Kalman Filtering using MMAlpha. In International Conference on Parallel Computing in Electrical Engineering (PARELEC 98), Bialystok, Poland, pages 201-206, September 1998. [WWW]


  24. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, and T. Risset. Derivation of Systolic Algorithms for The Algebraic Path Problem by Recurrence Transformations. In M. Tchuente, editor, 4ème Colloque Africain sur la Recherche Informatique, Dakar, Sénégal, pages 551,564, October 1998. Presse Universitaire de Dakar.


  25. F. Dupont de Dinechin, T. Risset, and S. Robert. Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. In Internationnal Conference on Parallel Computing (PARCO), 1997. North Holland. [WWW]


  26. P. Le Moenner, L. Perraudeau, S. Rajopadhye, T. Risset, and P. Quinton. Generating Regular Arithmetic Circuits with AlpHard. In Massively Parallel Computing Systems (MPCS'96), May 1996. [WWW]


  27. P. Quinton, S. V. Rajopadhye, and T. Risset. Extension of the Alpha Language to Recurrences on Sparse Periodic Domains. In J. Fortes et al., editor, International Conference on Application Specific Array Processors (ASAP), Chicago, Illinois, pages 391-401, 1996. IEEE Computer Society Press. [WWW]


  28. P.Y. Calland and T. Risset. Precise Tiling for Uniform Loop Nests. In C. Mongenet et al., editor, Application Specific Array Processors, pages 330-337, 1995. IEEE Computer Society Press. [WWW]


  29. M. Dion, T. Risset, and Y. Robert. Resource-Constrained Scheduling of Partitioned Algorithms on Processor Arrays. In EuroMicro Workshop on Parallel and Distributed Processing, pages 571-580, 1995. IEEE Computer Society Press.


  30. F Dupont De Dinechin, P. Quinton, and T. Risset. Structuration of the Alpha Language. In W.K. Giloi, S. Jahnichen, and B.D. Shriver, editors, Massively Parallel Programming Models, pages 18-24, 1995. IEEE Computer Society Press. [WWW]


  31. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. In Scalable High Performance Computing Conference (SHPCC'94), pages 568-576, 1994. IEEE Computer Society Press.


  32. T. Risset. Applying Semi-Systolic Techniques to SIMD Programming. In C. Girault, editor, Applications in Parallel and Distributed Computing (IFIP Transactions), pages 103-112, 1994. North-Holland. [WWW]


  33. A. Darte, T. Risset, and Y. Robert. Loop Nest Scheduling and Transformations. In J.J. Dongarra et al., editor, Environments and Tools for Parallel Scientific Computing, volume 6 of Advances in Parallel Computing, pages 309-332, 1993. North-Holland.


  34. T. Risset and S. Song. A Real Time Systolic Algorithm for On-the-fly Hidden Surface Removal. In L. Dadda and B. Wah., editors, Application Specific Array Processors, pages 238-249, 1993. IEEE Computer Society Press.


  35. T. Risset. A Method to Synthesize Modular Systolic Arrays with Local Broadcast Facility. In J. Fortes et al., editor, Application Specific Array Processors, pages 415-428, 1992. IEEE Computer Society Press.


  36. A. Darte, T. Risset, and Y Robert. Synthesizing Systolic Arrays: Some Recent Developments. In M. Valero et al., editor, Application Specific Array Processors, pages 372-386, 1991. IEEE Computer Society Press.


  37. A. Darte, Y. Robert, and T. Risset. Systolic Systems. In P.J. Hargraven, editor, 2nd IEE International Specialist Seminar on Parallel Digital Processors, volume 334 of IEEE Conference Publication, pages 6-10, 1991. IEEE Press.


  38. T. Risset. Linear Systolic Arrays for Matrix Multiplication: Comparisons of Existing Methods and New Results. In Proc. 2nd Workshop on Algorithms and VLSI parallel architecture, 1991.


  39. T. Risset and Y. Robert. Uniform but Non-Local DAGs: A Trade-off between Pure Systolic and SIMD Solutions. In M. Valero et al., editor, Application Specific Array Processors, pages 296-308, 1991. IEEE Computer Society Press.


Internal reports
  1. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. Technical report 2005-15, LIP, ENS-Lyon, April 2005.


  2. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Analysis and Synthesis of Cycle-Accurate On-Chip Traffic with Long-Range Dependence. Technical report 2005-53, LIP, ENS-Lyon, December 2005.


  3. D. Cachera, S. Rajopadhye, T. Risset, and C. Tadonki. Parallelization of the Algebraic Path Problem on Linear SIMD/SPMD Arrays. Technical report 1346, Irisa, 2000. [WWW]


  4. S.P.K. Nookala and T. Risset. A Library for Z-polyhedral Operations. Technical report 1330, Irisa, 2000. [WWW]


  5. F. Bardoult, P. Quinton, S. Rajopadhye, and T. Risset. Synthesis of Data-Flow Interfaces for Regular Parallel Programs. Technical report 1260, Irisa, September 1999. [WWW]


  6. F. Dupont de Dinechin, P. Quinton, S. Rajopadhye, and T. Risset. First Steps in Alpha. Technical report 1244, Irisa, 1999. [WWW]


  7. T. Risset, F. Dupont de Dinechin, and S. Robert. Structured Scheduling of Recurrence Equations. Technical report 1140, IRISA, 1997. [WWW]


  8. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. Technical report RR93-36, LIP, ENS-Lyon, November 1993.


  9. Alain Darte, Tanguy Risset, and Yves Robert. Synthesizing Systolic Arrays: Some Recent Developments. Technical report RR91-09, LIP, ENS-Lyon, France, 1991.


Miscellaneous
  1. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. Design, Automation and Test in Europe (DATE'04), University Booth Demonstration, February 2004.


  2. A.C. Guillou, P Quinton, T. Risset, C. Wagner, and D Massicotte. High Level Design of Digital Filters in Mobile Communications. DATE Design Contest 2001, March 2001. Note: Second place. [WWW]


  3. P. Quinton and T. Risset. MMAlpha: A Toolbox for Silicon Compilation. University Booth Demonstration, March 2000. Note: University booth stand.



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Last modified: Tue Dec 30 15:51:03 2014
Author: darte.

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