1. Alain Darte and Alexandre Isoard. Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes. In Björn Franke, editor, 24th International Conference on Compiler Construction (CC'15), Lecture Notes in Computer Science, London, UK, April 2015. Springer.



2. Paul Feautrier. The Power of Polynomials. In Alain Darte and Alexandra Jimborean, editors, 5th International Workshop on Polyhedral Compilation Techniques (IMPACT'15), Amsterdam, The Netherlands, January 2015.

1. Alain Darte and Alexandre Isoard. Parametric Tiling with Inter-Tile Data Reuse. In Sanjay Rajopadhye and Sven Verdoolaege, editors, 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, January 2014.



2. Paul Feautrier, Eric Violard, and Alain Ketterlin. Improving X10 Program Performance by Clock Removal. In Albert Cohen, editor, 23rd International Conference on Compiler Construction (CC'14), volume 8409 of Lecture Notes in Computer Science, Grenoble, France, pages 113-132, April 2014. Springer.



3. Guillaume Iooss, Christophe Alias, and Sanjay Rajopadhye. On Program Equivalence with Reductions. In 21st International Static Analysis Symposium (SAS'14), Munich, Germany, September 2014.



4. Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, and Yun Zou. CART: Constant Aspect Ratio Tiling. In Sanjay Rajopadhye and Sven Verdoolaege, editors, 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, January 2014.



5. Henrique Nazaré, Izabela Maffra, Willer Santos, Leonardo Oliveira, Fernando Pereira, and Laure Gonnord. Validation of Memory Accesses Through Symbolic Analyses. In OOPSLA, Portland, Oregon, United States, October 2014. [WWW]



6. Raphael Ernani Rodrigues, Péricles Alves, Fernando Pereira, and Laure Gonnord. Real-World Loops are Easy to Predict: A Case Study. In Workshop on Software Termination, Vienne, Autriche, July 2014. [WWW]



7. André Tavares, Fabrice Rastello, Benoit Boissinot, and Fernando Pereira. Parameterized Construction of Program Representations for Sparse Dataflow Analyses. In Albert Cohen, editor, 23rd International Conference on Compiler Construction (CC'14), volume 8409, Grenoble, France, April 2014. Springer. [WWW]

1. Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Rank: A Tool to Check Program Termination and Computational Complexity. In International Workshop on Constraints in Software Testing Verification and Analysis (CSTVA'13), Luxembourg, pages 238, March 2013. [WWW]



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In Design, Automation & Test in Europe (DATE'13), Grenoble, France, pages 575-580, March 2013.



3. Boubacar Diouf, Albert Cohen, and Fabrice Rastello. A Polynomial Spilling Heuristic: Layered Allocation. In International Symposium on Code Generation and Optimization (CGO'13), Shenzhen, China, pages 1-10, February 2013. IEEE Computer Society.



4. Guillaume Iooss, Sanjay Rajopadhye, and Christophe Alias. Semantic Tiling. In International Workshop on Leveraging Abstractions and Semantics in High-performance Computing (LASH-C), 2013.



5. Tomofumi Yuki, Paul Feautrier, Sanjay V. Rajopadhye, and Vijay Saraswat. Array Dataflow Analysis for Polyhedral X10 Programs. In 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, pages 23-34, February 2013. ACM.

1. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), New Orleans, USA, pages 285-286, February 2012. IEEE Computer Society. Note: Short paper.



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), Paris, January 2012. Note: PPoPP'12 extended version.



3. Guillaume Andrieu, Christophe Alias, and Laure Gonnord. SToP: Scalable Termination Analysis of (C) Programs (Tool Presentation). In International Workshop on Tools for Automatic Program Analysis (TAPAS'12), Deauville, France, September 2012.



4. Florian Brandner and Quentin Colombet. Copy Elimination on Data Dependence Graphs. In 27th Annual ACM Symposium on Applied Computing (SAC'12), Trento, Italy, pages 1916-1918, March 2012. ACM Press.



5. Paul Feautrier. Approximating the Transitive Closure of a Boolean-Affine Relation. In 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), Paris, January 2012.

1. Christophe Alias, Bogdan Pasca, and Alexandru Plesco. Automatic Generation of FPGA-Specific Pipelined Accelerators. In 7th International Symposium on Applied Reconfigurable Computing (ARC'11), Belfast, UK, pages 53-66, March 2011. Springer Verlag.



2. Benoit Boissinot, Florian Brandner, Alain Darte, Benoit Dupont de Dinechin, and Fabrice Rastello. A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. In 9th Asian Symposium on Programming Languages and Systems (APLAS'11), pages 137-154, December 2011. Springer Verlag.



3. Florian Brandner and Alain Darte. Compiler-driven Optimization of the Worst-Case Execution Time. In Laure Gonnord and David Monniaux, editors, Workshop ``Analyse to Compile, Compile to Analyse'' (ACCA'11), held with CGO'11, Chamonix, April 2011.



4. Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, and Fabrice Rastello. Graph Coloring and Treescan Register Allocation Using Repairing. In International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, October 2011. IEEE Computer Society.



5. Quentin Colombet, Florian Brandner, and Alain Darte. Studying Optimal Spilling in the Light of SSA. In International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, pages 25-34, October 2011. IEEE Computer Society.



6. Julien Le Guen, Christophe Guillon, and Fabrice Rastello. MinIR, a Minimalistic Intermediate Representation. In Florent Bouchez, Sebastian Hack, and Eelco Visser, editors, Workshop on Intermediate Representations (WIR'11), held with CGO'11, Chamonix, pages 5-12, April 2011.



7. André Tavares, Quentin Colombet, Mariza Bigonha, Christophe Guillon, Fernando Pereira, and Fabrice Rastello. Decoupled Graph-Coloring Register Allocation with Hierarchical Aliasing. In 14th International Workshop on Software & Compilers for Embedded Systems (SCOPES'11), St. Goar, Germany, pages 1-10, June 2011. ACM Press.



8. Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco. An FPGA Architecture for Solving the Table Maker's Dilemma. In 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'11), Santa Monica, CA, September 2011. IEEE Computer Society.

1. Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs. In 17th International Static Analysis Symposium (SAS'10), Perpignan, France, pages 117-133, September 2010. ACM press.



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-Level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool. In 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Rennes, France, pages 329-332, July 2010. IEEE Computer Society.



3. Florent Bouchez, Quentin Colombet, Alain Darte, Christophe Guillon, and Fabrice Rastello. Parallel Copy Motion. In 13th International Workshop on Software & Compilers for Embedded Systems (SCOPES'10), St. Goar, Germany, pages 1-10, June 2010. ACM Press.



4. Florian Brandner. Completeness of Automatically Generated Instruction Selectors. In 21st International Conference on Application-specific Systems Architectures and Processors (ASAP'10), Rennes, France, pages 175-182, July 2010. IEEE Computer Society.



5. Florian Brandner, Viktor Pavlu, and Andreas Krall. Execution Models for Processors and Instructions. In 28th Norchip Conference (NORCHIP'10), November 2010.



6. Alain Darte. Understanding Loops: The Influence of the Decomposition of Karp, Miller, and Winograd. In 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'10), Grenoble, France, pages 139-148, July 2010. IEEE Computer Society. Note: Invited paper.



7. Boubacar Diouf, Albert Cohen, Fabrice Rastello, and John Cavazos. Split Register Allocation: Linear Complexity Without the Performance Penalty. In International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'10), volume 5952 of Lecture Notes in Computer Science, pages 66-80, January 2010. Springer Verlag.



8. Paul Feautrier and Laure Gonnord. Accelerated Invariant Generation for C Programs with Aspic and C2fsm. In Workshop on Tools for Automatic Program Analysis (TAPAS'10), volume 267 of Electronic Notes in Theoretical Computer Science, pages 3-13, September 2010. [doi:10.1016/j.entcs.2010.09.014]

1. Benoit Boissinot, Alain Darte, Benoît Dupont de Dinechin, Christophe Guillon, and Fabrice Rastello. Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency. In International Symposium on Code Generation and Optimization (CGO'09), pages 114-125, March 2009. IEEE Computer Society Press. Note: Best paper award.



2. L. Gonnord and J.-P. Babau. Quantity of Resource Properties Expression and Runtime Assurance for Embedded Systems. In ACS/IEEE International Conference on Computer Systems and Applications (AICCSA'09), Rabbat, Morocco, pages 428-435, May 2009.



3. Ouassila Labbani, Paul Feautrier, Eric Lenormand, and Michel Barreteau. Elementary Transformation Analyses for Array-OL. In ACS/IEEE International Conference on Computer Systems and Applications (AICCSA'09), Rabat, Morocco, pages 362-367, May 2009.



4. Qingda Lu, Christophe Alias, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, and Tin-fook Ngai. Data Layout Transformation for Enhancing Locality on NUCA Chip Multiprocessors. In International ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT'09), pages 348-357, September 2009. ACM Press.



5. Marie Rastello, Fabrice Rastello, Hervé Bellot, Frédéric Ousset, and François Dufour. Size of Snow Particles in a Powder-Snow Avalanche. In ASME Fluids Engineering Division Summer Meeting 2009 (FEDSM'09), August 2009.

1. Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, and Fabrice Rastello. Fast Liveness Checking for SSA-Form Programs. In Sixth Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'08), Boston, MA, USA, pages 35-44, April 2008. ACM Press. Note: Best paper award.



2. Florent Bouchez, Alain Darte, and Fabrice Rastello. Advanced Conservative and Optimistic Register Coalescing. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'08), Atlanta, GA, USA, pages 147-156, October 2008. ACM Press.



3. Nicolas Farrugia, Michel Paindavoine, and Clément Quinson. On the Need for Semi-Automated Source-to-Source Transformations in the User-Guided High-Level Synthesis Tool. In High-Level Synthesis: Back to the Future (DAC workshop), June 2008. Note: Poster.



4. Alexandru Plesco and Tanguy Risset. Coupling Loop Transformations and High-Level Synthesis. In SYMPosium en Architectures nouvelles de machines (SYMPA'08), February 2008.

1. Christophe Alias, Fabrice Baray, and Alain Darte. Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 73-82, June 2007. ACM Press.



2. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Register Coalescing. In International Symposium on Code Generation and Optimization (CGO'07), pages 102-114, March 2007. IEEE Computer Society Press. Note: Best paper award.



3. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Spill Everywhere under SSA Form. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 103-112, June 2007. ACM Press.



4. G. Chelius, A. Fraboulet, and E. Fleury. Worldsens: A Fast and Accurate Development Framework for Sensor Network Applications. In The 22nd Annual ACM Symposium on Applied Computing (SAC 2007), Seoul, Korea, March 2007. ACM.



5. Hadda Cherroun and Paul Feautrier. An Exact Resource Constrained-Scheduler using Graph Coloring Technique. In The 5th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA'07), pages 554-561, May 2007. IEEE Computer Society. Note: Best paper award.



6. Alain Darte and Clément Quinson. Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. In The 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'07), pages 554-561, July 2007. IEEE Computer Society.



7. Nicolas Fournel, Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Bruno Allard, and Olivier Brevet. Worldsens: Embedded Sensor Network Application Development and Deployment. In 26th Annual IEEE Conference on Computer Communications (Infocom), Anchorage, Alaska, USA, May 2007. IEEE.



8. Nicolas Fournel, Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Bruno Allard, and Olivier Brevet. Worldsens: From Lab to Sensor Network Application Development and Deployment. In International Conference on Information Processing in Sensor Networks (IPSN), demo session, Cambridge, Massachusetts, USA., April 2007. ACM.



9. Nicolas Fournel, Antoine Fraboulet, and Paul Feautrier. Fast and Instruction Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements. In PATMOS Workshop - International Workshop on Power And Timing Modeling, Optimization and Simulation, Göteborg, Sweden, September 2007.



10. Nicolas Fournel, Antoine Fraboulet, and Paul Feautrier. eSimu : a Fast and Accurate Energy Consumption Simulator for Embedded Systems. In IEEE International Workshop: From Theory to Practice in Wireless Sensor Networks, Helsinki, Finland, June 2007.



11. N. Fournel, M. Minier, and S. Ubéda. Survey and Benchmark of Stream Ciphers for Wireless Sensor Networks. In Workshop in Information Security Theory and Practices (WISTP 2007), Heraklion, Crete, Greece, May 2007.



12. Antoine Fraboulet, Guillaume Chelius, and Eric Fleury. Worldsens: Development and Prototyping Tools for Application Specific Wireless Sensors Networks. In IPSN'07 Track on Sensor Platforms, Tools and Design Methods (SPOTS), Cambridge, Massachusetts, USA., April 2007. ACM.



13. Daniel Grund and Sebastian Hack. A Fast Cutting-Plane Algorithm for Optimal Coalescing. In Shriram Krishnamurthi and Martin Odersky, editors, Compiler Construction (CC'07), volume 4420 of Lecture Notes In Computer Science, pages 111-125, March 2007. Springer. Note: Best paper award. [WWW]

1. P. Amiranoff, A. Cohen, and P. Feautrier. Beyond Iteration Vectors: Instancewise Relational Abstract Domains. In Static Analysis Symposium (SAS'06), Seoul, Corea, August 2006.



2. P. Borgnat, N. Larrieu, P. Owezarski, P. Abry, J. Aussibal, L. Gallon, G. Dewaele, N. Nobelis, L. Bernaille, A. Scherrer, Y. Zhang, Y. Labit, and et al.. Détection d'attaques de dénis de service par un modèle non gaussien multirésolution. In Colloque francophone sur l'ingénierie des protocoles (CFIP), Tozeur, Tunisie, November 2006.



3. Florent Bouchez, Alain Darte, Christophe Guillon, and Fabrice Rastello. Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove?. In Annual Workshop in Duplicating, Deconstructing, and Debunking (WDDD'06), held in conjunction with the International Symposium on Computer Architecture (ISCA'33), Boston, MA, USA, July 2006.



4. Florent Bouchez, Alain Darte, Christophe Guillon, and Fabrice Rastello. Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How. In International Workshop on Languages and Compilers for Parallel Computing (LCPC'06), New Orleans, FL, USA, November 2006. Springer Verlag.



5. Guillaume Chelius, Antoine Fraboulet, and Eric Fleury. Demonstration of Worldsens: A Fast Prototyping and Performance Evaluation Tool for Wireless Sensor Network Applications & Protocols. In Second International Workshop on Multi-hop Ad Hoc Networks: From Theory to Reality (REALMAN), Firenze, Italia, pages 131 - 133, May 2006. ACM.



6. Hadda Cherroun, Alain Darte, and Paul Feautrier. Scheduling under Resource Constraints using Dis-Equalities. In Design Automation and Test in Europe (DATE'06), March 2006.



7. Antoine Fraboulet, Guillaume Chelius, and Eric Fleury. Worldsens: System Tools for Embedded Sensor Networks. In Real-Time Systems Symposium (RTSS 2006) (Work in Progress), Rio de Janeiro, Brasil, December 2006. IEEE.



8. Philippe Grosse, Yves Durand, and Paul Feautrier. Power Modeling of a NoC Based Design for High-Speed Telecommunication Systems. In 16th PATMOS Workshop - International Workshop on Power And Timing Modeling, Optimization and Simulation, Montpellier, France, September 2006.



9. Silvius Rus, Guobin He, Christophe Alias, and Lawrence Rauchwerger. Region Array SSA. In 15th International Conference on Parallel Architectures and Compilation Techniques (PACT'06), Seattle, WA, USA, pages 43-52, September 2006.



10. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. A Generic Multi-Phase On-Chip Traffic Generation Environment. In IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs, Colorado, USA, September 2006.



11. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Automatic Phase Detection for Stochastic On-Chip Traffic Generation. In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), seoul, South Corea, pages 88 - 93, October 2006. ACM Press.



12. Antoine Scherrer, Nicolas Larrieu, Pierre Borgnat, Philippe Owezarski, and Patrice Abry. Non Gaussian and Long Memory Statistical Modeling of Internet Traffic. In 4th International Workshop on Internet Performance, Simulation, Monitoring and Measurement (IPS MOME), Salzbourg, Austria, March 2006. [WWW]



13. Antoine Scherrer, Nicolas Larrieu, Pierre Borgnat, Philippe Owezarski, and Patrice Abry. Une caractérisation non gaussienne et longue mémoire du trafic Internet et de ses anomalies. In 5th Conference on Security and Network Architectures (SAR), Seignosse, France, June 2006. [WWW]

1. Christophe Alias. TeMa: an Efficient Tool to find High-Performance Library Patterns in Source Code. In International Workshop on Patterns in High-Performance Computing, 2005.



2. Christophe Alias and Denis Barthou. Deciding Where to Call Performance Libraries. In International IEEE/ACM Euro-Par Conference, 2005.



3. Christophe Alias and Denis Barthou. On Domain Specific Languages Re-Engineering. In International ACM Conference on Generative Programming and Component-based Engineering, 2005.



4. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. In IEEE International Conference on Application-Specific Systems, Architecture, and Processors (ASAP'05), pages 28-35, 2005. IEEE Computer Society Press.



5. Alain Darte and Robert Schreiber. A Linear-Time Algorithm for Optimal Barrier Placement. In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'05), Chicago, IL, USA, pages 26-35, June 2005.

1. Cédric Bastoul and Paul Feautrier. More Legal Transformations for Locality. In Euro-Par'04, volume LNCS 3149, pages 272-283, 2004. Springer Verlag. Note: Distinguished Paper Award.



2. Paul Feautrier. Scalable and Modular Scheduling. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architectures, Modeling and Simulation (SAMOS 2004), volume LNCS 3133, pages 433-442, July 2004. Springer Verlag.



3. Antoine Fraboulet and Tanguy Risset. Efficient On-Chip Communications for Data-Flow IPs. In Application-Specific Systems, Architectures, and Processors (ASAP'04), pages 293-303, 2004. IEEE Computer Society Press.



4. Christophe Guillon, Fabrice Rastello, Thierry Bidault, and Florent Bouchez. Procedure Placement using Temporal-Ordering Information: Dealing with Code Size Expansion. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), pages 268-279, 2004. ACM Press.



5. Fabrice Rastello, Francois de Ferrière, and Christophe Guillon. Optimizing Translation Out of SSA using Renaming Constraints. In International Symposium on Code Generation and Optimization (CGO'04), pages 265-278, March 2004. IEEE Computer Society Press.



6. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architecture, Modeling, and Simulation (SAMOS 2004), volume 3133 of LNCS, pages 453-462, July 2004. Springer Verlag.



7. Antoine Scherrer, Tanguy Risset, and Antoine Fraboulet. Hardware Wrapper Classification and Requirements for On-Chip Interconnects. In Signaux, Circuits et Systèmes 2004, Monastir, Tunisie, pages 31-34, March 2004.

1. Christophe Alias and Denis Barthou. Algorithm Recognition based on Demand-Driven Dataflow Analysis. In International IEEE Working Conference on Reverse Engineering, 2003.



2. Christophe Alias and Denis Barthou. On the Recognition of Algorithm Templates. In Electronic Notes in Theoretical Computer Science, editor, International Workshop on Compiler Optimization meets Compiler Verification, volume 82, April 2003. ETAPS.



3. A. Darte, R. Schreiber, and G. Villard. Lattice-Based Memory Allocation. In 6th ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES'03), San Jose, CA, USA, pages 298-308, October 2003.



4. A.-C. Guillou, P. Quinton, and T. Risset. Hardware Synthesis for Multi-Dimensional Time. In IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 2003.



5. Antoine Scherrer and Antoine Fraboulet. Étude de la couche transport des réseaux sur puce. In Symposium en Architecture et Adéquation Algorithme Architecture (SympAAA), La Colle sur Loup, France, October 2003.

1. Denis Barthou, Paul Feautrier, and Xavier Redon. On the Equivalence of Two Systems of Affine Recurrence Equations. In European Conference on Parallel Computing (Euro-Par 2002), volume 2400 of LNCS, Paderborn, Germany, pages 309-313, August 2002. Springer Verlag.



2. D. Cachera and T. Risset. Advances in Bit Width Selection Methodology. In IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, July 2002. [WWW]



3. Daniel Chavarría-Miranda, Alain Darte, Robert Fowler, and John Mellor-Crummey. Generalized Multipartitioning for Multi-Dimensional Arrays. In 16th International Parallel and Distributed Processing Symposium (IPDPS'02), Fort Lauderdale, Florida, April 2002. IEEE Computer Society Press. Note: « Best paper award ».



4. Albert Cohen, Daniela Genius, Abdesselem Kortebi, Zbigniew Chamski, Marc Duranton, and Paul Feautrier. Multiperiodic Process Networks: Prototyping and Verifying Stream-Processing Systems. In European Conference on Parallel Computing (Euro-Par 2002), volume 2400 of LNCS, Paderborn, Germany, pages 137-146, August 2002. Springer Verlag.



5. A. Darte and G. Huard. Complexity of Multi-Dimensional Loop Alignment. In 19th International Symposium on Theoretical Aspects of Computer Science (STACS'02), volume 2285, pages 179-191, March 2002. Springer Verlag.



6. A. Darte and G. Huard. New Results on Array Contraction. In 13th International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pages 359-370, July 2002. IEEE Computer Society Press.



7. Thierry Dauxois and Fabrice Rastello. Efficient Tiling for an ODE Discrete Integration Program: Redundant Tasks Instead of Trapezoidal-Shaped Tiles. In Workshop on Massively Parallel Processing (WMPP 2002), Fort Lauderdale, Florida, April 2002. IEEE Computer Society Press.



8. S. Derrien, A. C. Guillou, P. Quinton, T. Risset, and C Wagner. Automatic Synthesis of Efficient Interfaces for Compiled Regular. In International Samos Workshop on Systems, Architectures, Modeling and Simulation (Samos), Samos, Grèce, July 2002. [WWW]



9. F. Dupont de Dinechin, M. Manjunathaiah, T. Risset, and M. Spivey. Design of Highly Parallel Architectures with Alpha and Handel. In Forum on Specification and Design Languages (FDL 2002), Marseille, September 2002. [WWW]



10. Antoine Fraboulet and Anne Mignotte. Optimisation de la mémoire et de la consommation des systèmes multimédia embarqués. In Colloque CAO de circuits intégrés et systèmes, Paris, pages 177-180, May 2002.



11. Martin Griebl, Paul Feautrier, and Armin Groesslinger. Forward Communication Only Placements. In 15th Workshop on Languages and Compilers for Parallel Computing (LCPC 2002), July 2002.



12. R. Huaulme, J.-P. Babau, and A. Mignotte. Java Data Flow for Real-Time HW/SW Synthesis of Mobile Devices. In Forum on Specification and Design Languages (FDL 2002), Marseille, September 2002.



13. Peng Wu, Paul Feautrier, David Padua, and Zehra Sura. Instance-wise Points-to Analysis for Loop-based Dependence Testing. In International Conference on Supercomputing (ISC'02), pages 262 - 273, June 2002.

1. Olivier Beaumont, Vincent Boudet, Arnaud Legrand, Fabrice Rastello, and Yves Robert. Heterogeneous Matrix-Matrix Multiplication, or Partitioning a Square into Rectangles: NP-Completeness and Approximation Algorithms. In EuroMicro Workshop on Parallel and Distributed Computing (EuroMicro 2001), pages 298-305, 2001. IEEE Computer Society Press.



2. D. Cachera, P. Quinton, S. Rajopadhye, and T. Risset. Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. In 6th International Workshop on Formal Methods for Parallel Programming: Theory and Applications (FMPPTA), San Francisco, April 2001. [WWW]



3. Benoît Dupont de Dinechin, Christophe Monat, and Fabrice Rastello. Parallel Execution of the Saturated Reductions. In Workshop on Signal Processing Systems (SIPS 2001), pages 373-384, 2001. IEEE Computer Society Press.



4. Antoine Fraboulet, Karen Godary, and Anne Mignotte. Loop Fusion for Memory Space Optimization. In International Symposium on System Synthesis (ISSS'01), Montréal, Canada, pages 95-100, October 2001. IEEE Press.



5. Antoine Fraboulet, Laurence Just-Meunier, and Anne Mignotte. Memory Optimization of Data Flow Applications at the Codesign Level. In Cadence Technical Conference, San Jose, USA, April 2001.



6. Antoine Fraboulet and Anne Mignotte. Source Code Loop Transformations for Memory Hierarchy Optimizations. In MEDEA 2001, Barcelone, Spain, September 2001. [PDF]



7. A.-C. Guillou, F. Quilleré, P. Quinton, S. Rajopadhye, and T. Risset. Hardware Design Methodology with the Alpha Language. In FDL'01, Lyon, France, September 2001. [WWW]



8. M Manjunathaiah, G. M. Megson, T. Risset, and S. Rajopadhye. Uniformization of Affine Dependence Programs for Parallel Embedded System Design. In L.M. Ni and M. Valero, editors, International Conference on Parallel Processing, Valencia, Spain, pages 205-213, 2001. [WWW]



9. P. Quinton and T. Risset. Structured Scheduling of Recurrence Equations: Theory and Practice. In Proc. of the System Architecture MOdelling and Simulation Workshop, Lecture Notes in Computer Science, Samos, Greece, 2001. Springer Verlag. [WWW]

1. Olivier Beaumont, Vincent Boudet, Arnaud Legrand, Fabrice Rastello, and Yves Robert. Dense Linear Algebra Kernels on Heterogeneous Platforms. In International Workshop on Parallel Matrix Algorithms and Applications, Neuchâtel, Suisse, August 2000.



2. Olivier Beaumont, Vincent Boudet, Arnaud Legrand, Fabrice Rastello, and Yves Robert. Heterogeneity Considered Harmful to Algorithm Designers. In Cluster 2000, pages 403-404, 2000. IEEE Computer Society Press.



3. Olivier Beaumont, Vincent Boudet, Fabrice Rastello, and Yves Robert. Load Balancing Strategies for Dense Linear Algebra Kernels on Heterogeneous Two-dimensional Grids. In 14th International Parallel and Distributed Processing Symposium (IPDPS 2000), Mexico, pages 783-792, 2000. IEEE Computer Society Press.



4. Olivier Beaumont, Vincent Boudet, Fabrice Rastello, and Yves Robert. Matrix-Matrix Multiplication on Heterogeneous Platforms. In International Conference on Parallel Processing (ICPP 2000), pages 289-298, 2000. IEEE Computer Society Press.



5. A. Darte, C. Diderich, M. Gengler, and F. Vivien. Scheduling the Computations of a Loop Nest with Respect to a Given Mapping. In European Conference on Parallel Computing (Euro-Par'00), volume 1900 of LNCS, München, Germany, pages 405-414, August 2000. Springer Verlag.



6. A. Darte, R. Schreiber, B. R. Rau, and F. Vivien. A Constructive Solution to the Juggling Problem in Systolic Array Synthesis. In International Parallel and Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, pages 815-821, May 2000.



7. A. Darte and G.-A. Silber. Temporary Arrays for Distribution of Loops with Control Dependences. In European Conference on Parallel Computing (Euro-Par'00), volume 1900 of LNCS, München, Germany, pages 357-367, August 2000. Springer Verlag.



8. S. Derrien and T. Risset. Interfacing compiled FPGA programs: the MMAlpha approach. In A. Arabnia, editor, PDPTA2000: Second International Workshop on Engineering of Reconfigurable Hardware/Software Objects, June 2000. CSREA Press. [WWW]



9. Antoine Fraboulet, Laurence Just-Meunier, and Anne Mignotte. Memory Optimization of Data Flow Applications at the Codesign Level. In Sophia Antipolis Forum on Microelectronics (SAME), Sophia Antipolis, France, pages 16-21, October 2000. [PDF]



10. A.C. Guillou, P. Quinton, and T. Risset. Automatic Design of VLSI Pipelined LMS Architectures. In 2000 IEEE Canadian Conference on Electrical and Computer Engineering, Trois Rivières, Canada, August 2000. [WWW]

1. Vincent Boudet, Antoine Petitet, Fabrice Rastello, and Yves Robert. Data Allocation Strategies for Dense Linear Algebra Kernels on Heterogeneous Two-Dimensional Grids. In Parallel and Distributed Computing and Systems conference (PDCS'99), pages 561-569, 1999. IASTED Press.



2. Vincent Boudet, Fabrice Rastello, and Yves Robert. A Proposal for a Heterogeneous Cluster ScaLAPACK (Dense Linear Solvers). In Hamid R. Arabnia, editor, International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), pages 1285-1291, 1999. CSREA Press.



3. Vincent Boudet, Fabrice Rastello, and Yves Robert. Algorithmic Issues for (Distributed) Heterogeneous Computing Platforms. In Rajkumar Buyya and Toni Cortes, editors, Cluster Computing Technologies, Environments, and Applications (CC-TEA'99), pages 709-712, 1999. CSREA Press.



4. Vincent Boudet, Fabrice Rastello, and Yves Robert. PVM Implementation of Heterogeneous ScaLAPACK Dense Linear Solvers. In J. Dongarra, E. Luque, and T. Margalef, editors, Recent Advances in Parallel Virtual Machine and Message Passing Interface, LNCS 1697, pages 333-340, 1999. Springer Verlag.



5. Alain Darte. On the Complexity of Loop Fusion. In International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pages 149-157, October 1999.



6. Alain Darte and Guillaume Huard. Loop Shifting for Loop Compaction. In Languages and Compilers for Parallel Computing (LCPC'99), volume 1863 of Lecture Notes in Computer Science, pages 415-431, August 1999. Springer Verlag.



7. Antoine Fraboulet, Guillaume Huard, and Anne Mignotte. Loop Alignment for Memory Accesses Optimization. In International Symposium on System Synthesis (ISSS'99), San Jose, Californie, pages 71-77, November 1999. IEEE Press. [PDF]



8. Antoine Fraboulet, Guillaume Huard, and Anne Mignotte. Optimisation de la consommation et de la place mémoire par transformations de boucles. In Colloque CAO de circuits intégrés et systèmes, Aix en Provence, pages 181-184, May 1999.



9. Martin Griebl, Paul Feautrier, and Christian Lengauer. On Index Set Splitting. In International Conference on Parallel Architectures and Compilation Techniques (PACT'99), 1999.



10. A. Mozipo, D. Massicote, P. Quinton, and T. Risset. A Parallel Architecture for Adaptative Channel Equalization Based On Kalman Filter Using MMAlpha. In 1999 IEEE Canadian Conference on Electrical and Computer Engineering, 1999.



11. E. Mémin and T. Risset. Full Alternate Jacobi Minimization and VLSI Derivation of Hardware for Motion Estimation. In International Workshop on Parallel Image Processing and Analysis, IWPIPA'99, Madras, India, January 1999. [WWW]



12. S. Rajopadhye, T. Risset, and C. Tadonki. The Algebraic Path Problem Revisited. In 5th International Euro-Par Conference, Toulouse, France, pages 698-707, August 1999. [WWW]



13. T. Risset and Y. Saouter. Synthèse de haut niveau d'un co-processeur pour le calcul des bases de Gröbner. In 5ème Symposium en architecture nouvelles de machines (Sympa'5), Rennes, June 1999. [WWW]



14. Georges-André Silber and Alain Darte. The Nestor Library: A Tool for Implementing Fortran Source to Source Transformations. In High Performance Computing and Networking (HPCN'99), volume 1593 of Lecture Notes in Computer Science, pages 653-662, April 1999. Springer Verlag.

1. S. Balev, P. Quinton, S. V. Rajopadhye, and T. Risset. Linear Programming Models for Scheduling Systems of Affine Recurrence Equations -- a Comparative Study --. In 10th ACM Symposium on Parallel Algorithms and Architectures (SPAA), 1998. [WWW]



2. Vincent Boudet, Fabrice Rastello, and Yves Robert. Alignment and Distribution is NOT (Always) NP-hard. In Chyi-Nan Chen and Lionel M. Ni, editors, ICPADS'98, Taiwan, pages 648-657, 1998. IEEE Computer Society Press.



3. A. Mozipo, D. Massicotte, P. Quinton, and T. Risset. Automatic Synthesis of a Parallel Architecture for Kalman Filtering using MMAlpha. In International Conference on Parallel Computing in Electrical Engineering (PARELEC 98), Bialystok, Poland, pages 201-206, September 1998. [WWW]



4. Fabrice Rastello, Amit Rao, and Santosh Pande. Optimal Task Scheduling to Minimize Inter-Tile Latencies. In International Conference on Parallel Processing (ICPP'98), pages 172-179, 1998. IEEE Computer Society Press.



5. Fabrice Rastello and Yves Robert. Loop Partitioning versus Tiling for Cache-Based Multiprocessors. In International Conference on Parallel and distributed Computing and Systems, PDCS'98, Las Vegas, pages 477-483, 1998. IASTED Press.



6. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, and T. Risset. Derivation of Systolic Algorithms for The Algebraic Path Problem by Recurrence Transformations. In M. Tchuente, editor, 4ème Colloque Africain sur la Recherche Informatique, Dakar, Sénégal, pages 551,564, October 1998. Presse Universitaire de Dakar.

1. Frédéric Desprez, Jack Dongarra, Fabrice Rastello, and Yves Robert. Determining the Idle Time of a Tiling: New Results. In Parallel Architectures and Compilation Techniques PACT'97, pages 307-317, 1997. IEEE Computer Society Press.



2. F. Dupont de Dinechin, T. Risset, and S. Robert. Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. In Internationnal Conference on Parallel Computing (PARCO), 1997. North Holland. [WWW]

1. T. Brandes, S. Chaumette, M.-C. Counilh, A. Darte, F. Desprez, J.C Mignot, and J. Roman. HPFIT and the TransTool Environment. In J. J. Dongarra and B. Tourancheau, editors, 3rd Workshop on Environments and Tools for Parallel Scientific Computing, August 1996. SIAM Press.



2. Pierre-Yves Calland, Alain Darte, and Yves Robert. A New Guaranteed Heuristic for the Software Pipelining Problem. In 1996 International Conference on Supercomputing (ICS'96), pages 261-269, 1996. ACM Press.



3. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. On the Removal of Anti and Output Dependences. In J. Fortes, C. Mongenet, K. Parhi, and V. Taylor, editors, Application Specific Systems, Architectures and Processors (ASAP'96), pages 353-364, 1996. IEEE Computer Science Press.



4. P.-Y. Calland, A. Darte, Y. Robert, and F. Vivien. Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms. In J. J. Dongarra and B. Tourancheau, editors, 3rd Workshop on Environments and Tools for Parallel Scientific Computing, August 1996. SIAM Press.



5. Alain Darte and Frédéric Vivien. On the Optimality of Allen and Kennedy's Algorithm for Parallelism Detection in Nested Loops. In Europar'96, volume 1123 of Lecture Notes in Computer Science, pages 379-388, August 1996. Springer Verlag.



6. Alain Darte and Frédéric Vivien. Optimal Fine and Medium Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs. In Parallel and Architectures and Compilation Techniques (PACT'96), pages 281-291, October 1996. IEEE Computer Society Press.



7. P. Le Moenner, L. Perraudeau, S. Rajopadhye, T. Risset, and P. Quinton. Generating Regular Arithmetic Circuits with AlpHard. In Massively Parallel Computing Systems (MPCS'96), May 1996. [WWW]



8. P. Quinton, S. V. Rajopadhye, and T. Risset. Extension of the Alpha Language to Recurrences on Sparse Periodic Domains. In J. Fortes et al., editor, International Conference on Application Specific Array Processors (ASAP), Chicago, Illinois, pages 391-401, 1996. IEEE Computer Society Press. [WWW]

1. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Heuristics for the Evaluation of Array Expressions on State-of-the-Art Massively Parallel Machines. In M. Moonen and F. Catthoor, editors, Algorithms and Parallel VLSI Architectures III, pages 319-330, 1995. North Holland.



2. P.Y. Calland and T. Risset. Precise Tiling for Uniform Loop Nests. In C. Mongenet et al., editor, Application Specific Array Processors, pages 330-337, 1995. IEEE Computer Society Press. [WWW]



3. Alain Darte, Michèle Dion, and Yves Robert. A Characterization of One-to-One Modular Mappings. In 7th IEEE Symposium on Parallel and Distributed Processing (SPDP'95), pages 382-389, 1995. IEEE Computer Science Press.



4. Alain Darte and Frédéric Vivien. A Classification of Nested Loops Parallelization Algorithms. In INRIA-IEEE Symposium on Emerging Technologies and Factory Automation (ETFA'95), pages 217-224, 1995. IEEE Computer Society Press.



5. Alain Darte and Frédéric Vivien. Revisiting the Decomposition of Karp, Miller and Winograd. In Application Specific Array Processors (ASAP'95), pages 13-25, 1995. IEEE Computer Society Press.



6. M. Dion, T. Risset, and Y. Robert. Resource-Constrained Scheduling of Partitioned Algorithms on Processor Arrays. In EuroMicro Workshop on Parallel and Distributed Processing, pages 571-580, 1995. IEEE Computer Society Press.



7. F Dupont De Dinechin, P. Quinton, and T. Risset. Structuration of the Alpha Language. In W.K. Giloi, S. Jahnichen, and B.D. Shriver, editors, Massively Parallel Programming Models, pages 18-24, 1995. IEEE Computer Society Press. [WWW]

1. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap. In B. Buchberger and J. Volkert, editors, Parallel Processing: CONPAR 94-VAPP VI, volume 854 of Lecture Notes in Computer Science, pages 713-724, 1994. Springer Verlag.



2. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. In Scalable High Performance Computing Conference (SHPCC'94), pages 568-576, 1994. IEEE Computer Society Press.



3. Alain Darte. Mapping Uniform Loop Nests onto Distributed Memory Architectures. In G. R. Joubert, D. Trystram, F. J. Peters, and D. J. Evans, editors, Parallel Computing: Trends and Applications, pages 287-294, 1994. Elsevier Science B.V..



4. Alain Darte and Yves Robert. The Alignment Problem for Perfect Uniform Loop Nest: NP-Completeness and Heuristics. In J. J. Dongarra and B. Tourancheau, editors, 2nd Workshop on Environments and Tools for Parallel Scientific Computing, pages 33-42, 1994. SIAM Press.



5. T. Risset. Applying Semi-Systolic Techniques to SIMD Programming. In C. Girault, editor, Applications in Parallel and Distributed Computing (IFIP Transactions), pages 103-112, 1994. North-Holland. [WWW]

1. A. Darte, T. Risset, and Y. Robert. Loop Nest Scheduling and Transformations. In J.J. Dongarra et al., editor, Environments and Tools for Parallel Scientific Computing, volume 6 of Advances in Parallel Computing, pages 309-332, 1993. North-Holland.



2. Alain Darte and Yves Robert. Communication-Minimal Mapping of Uniform Loop Nests onto Distributed Memory Architectures. In L. Dadda and B. Wah, editors, Application Specific Array Processors (ASAP'93), pages 1-14, 1993. IEEE Computer Society Press.



3. T. Risset and S. Song. A Real Time Systolic Algorithm for On-the-fly Hidden Surface Removal. In L. Dadda and B. Wah., editors, Application Specific Array Processors, pages 238-249, 1993. IEEE Computer Society Press.

1. Alain Darte. Two Heuristics for Task Scheduling. In Patrice Quinton and Yves Robert, editors, Algorithms and Parallel VLSI Architectures, volume 2, pages 383-388, 1992. Elsevier Science Publishers B.V..



2. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Close to Optimality. In J. A. B. Fortes, E. Lee, and T. Meng, editors, Application Specific Array Processors (ASAP'92), pages 37-46, 1992. IEEE Computer Society Press.



3. Alain Darte and Yves Robert. Scheduling Uniform Loop Nests. In R. Melhem, editor, ISMM Conference on Parallel and Distributed Systems, pages 75-82, 1992. ISMM Press.



4. Alain Darte and Yves Robert. Séquencement des nids de boucles. In Michel Cosnard, Maurice Nivat, and Yves Robert, editors, Algorithmique Parallèle, pages 343-368, 1992. Masson.



5. T. Risset. A Method to Synthesize Modular Systolic Arrays with Local Broadcast Facility. In J. Fortes et al., editor, Application Specific Array Processors, pages 415-428, 1992. IEEE Computer Society Press.

1. A. Darte, T. Risset, and Y Robert. Synthesizing Systolic Arrays: Some Recent Developments. In M. Valero et al., editor, Application Specific Array Processors, pages 372-386, 1991. IEEE Computer Society Press.



2. A. Darte, Y. Robert, and T. Risset. Systolic Systems. In P.J. Hargraven, editor, 2nd IEE International Specialist Seminar on Parallel Digital Processors, volume 334 of IEEE Conference Publication, pages 6-10, 1991. IEEE Press.



3. T. Risset. Linear Systolic Arrays for Matrix Multiplication: Comparisons of Existing Methods and New Results. In Proc. 2nd Workshop on Algorithms and VLSI parallel architecture, 1991.



4. T. Risset and Y. Robert. Uniform but Non-Local DAGs: A Trade-off between Pure Systolic and SIMD Solutions. In M. Valero et al., editor, Application Specific Array Processors, pages 296-308, 1991. IEEE Computer Society Press.

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