1. Alain Darte. Regular Partitioning for Synthesizing Fixed-Size Systolic Arrays. INTEGRATION, The VLSI Journal, 12:293-304, December 1991.



2. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Nearly Optimal. Parallel Processing Letters, 1(2):73-81, 1991.



3. T. Risset and Y. Robert. Synthesis of Processor Arrays for the Algebraic Path Problem: Unifying Old Results and Deriving New Architectures. Parallel Processing Letters, 1:19-28, 1991.

1. A. Darte, T. Risset, and Y Robert. Synthesizing Systolic Arrays: Some Recent Developments. In M. Valero et al., editor, Application Specific Array Processors, pages 372-386, 1991. IEEE Computer Society Press.



2. A. Darte, Y. Robert, and T. Risset. Systolic Systems. In P.J. Hargraven, editor, 2nd IEE International Specialist Seminar on Parallel Digital Processors, volume 334 of IEEE Conference Publication, pages 6-10, 1991. IEEE Press.



3. T. Risset. Linear Systolic Arrays for Matrix Multiplication: Comparisons of Existing Methods and New Results. In Proc. 2nd Workshop on Algorithms and VLSI parallel architecture, 1991.



4. T. Risset and Y. Robert. Uniform but Non-Local DAGs: A Trade-off between Pure Systolic and SIMD Solutions. In M. Valero et al., editor, Application Specific Array Processors, pages 296-308, 1991. IEEE Computer Society Press.

1. Alain Darte. Regular Partitioning for Synthesizing Fixed-Size Systolic Arrays. Technical report RR91-10, LIP, ENS-Lyon, France, 1991.



2. Alain Darte. Two Heuristics for Task Scheduling. Technical report RR91-30, LIP, ENS-Lyon, France, 1991.



3. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Nearly Optimal. Technical report RR91-35, LIP, ENS-Lyon, France, 1991.



4. Alain Darte, Tanguy Risset, and Yves Robert. Synthesizing Systolic Arrays: Some Recent Developments. Technical report RR91-09, LIP, ENS-Lyon, France, 1991.

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