1. Cédric Bastoul and Paul Feautrier. More Legal Transformations for Locality. In Euro-Par'04, volume LNCS 3149, pages 272-283, 2004. Springer Verlag. Note: Distinguished Paper Award.



2. Paul Feautrier. Scalable and Modular Scheduling. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architectures, Modeling and Simulation (SAMOS 2004), volume LNCS 3133, pages 433-442, July 2004. Springer Verlag.



3. Antoine Fraboulet and Tanguy Risset. Efficient On-Chip Communications for Data-Flow IPs. In Application-Specific Systems, Architectures, and Processors (ASAP'04), pages 293-303, 2004. IEEE Computer Society Press.



4. Christophe Guillon, Fabrice Rastello, Thierry Bidault, and Florent Bouchez. Procedure Placement using Temporal-Ordering Information: Dealing with Code Size Expansion. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), pages 268-279, 2004. ACM Press.



5. Fabrice Rastello, Francois de Ferrière, and Christophe Guillon. Optimizing Translation Out of SSA using Renaming Constraints. In International Symposium on Code Generation and Optimization (CGO'04), pages 265-278, March 2004. IEEE Computer Society Press.



6. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architecture, Modeling, and Simulation (SAMOS 2004), volume 3133 of LNCS, pages 453-462, July 2004. Springer Verlag.



7. Antoine Scherrer, Tanguy Risset, and Antoine Fraboulet. Hardware Wrapper Classification and Requirements for On-Chip Interconnects. In Signaux, Circuits et Systèmes 2004, Monastir, Tunisie, pages 31-34, March 2004.

1. Thierry Bidault, Christophe Guillon, Florent Bouchez, and Fabrice Rastello. Procedure Placement using Temporal-Ordering Information: Dealing with Code Size Expansion. Technical report RR-04-16, LIP, ENS Lyon, France, April 2004. [WWW]



2. Alain Darte and Rob Schreiber. Nested Circular Arc Families: A Model for Barrier Placement in Single-Program, Multiple-Data Codes with Nested Loops. Technical report RR2004-57, LIP, ENS-Lyon, December 2004.



3. Alain Darte, Rob Schreiber, and Gilles Villard. Lattice-Based Memory Allocation. Technical report RR2004-23, LIP, ENS-Lyon, April 2004.

1. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. Design, Automation and Test in Europe (DATE'04), University Booth Demonstration, February 2004.

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