1. Alain Darte and Serge Vaudenay. Algorithmique et optimisation: exercices corrigés, Sciences Sup. Dunod, 2001. Note: ISBN 2-10-005643-3.



2. Alain Darte, Yves Robert, and Frédéric Vivien. Scheduling and Automatic Parallelization. Birkhauser, 2000. Note: ISBN 0-8176-4149-1.



3. Guy-René Perrin and Alain Darte, editors. The Data Parallel Programming Model, volume 1132 of LNCS Tutorial. Springer Verlag, 1996.

1. Alain Darte. De l'organisation des calculs dans les codes répétitifs. Thèse d'habilitation à diriger des recherches, Université Claude Bernard de Lyon, December 1999. [WWW]



2. Alain Darte. Techniques de parallélisation automatique de nids de boucles. Thèse de doctorat, Université Claude Bernard de Lyon, April 1993. [WWW]

1. Quentin Colombet, Florian Brandner, and Alain Darte. Studying Optimal Spilling in the Light of SSA. ACM Transactions on Architecture and Code Optimization (ACM TACO), October 2014.



2. Benoit Boissinot, Philip Brisk, Alain Darte, and Fabrice Rastello. SSI Properties Revisited. ACM Transactions on Embedded Computing Systems, 11S(1), June 2012. Note: Article 21, 23 pages.



3. Alain Darte. Optimal Parallelism Detection in Nested Loops. In David Padua, editor, Encyclopedia of Parallel Programming. Springer, 2011.



4. Alain Darte. Quelques propriétés mathématiques et algorithmiques des ensembles convexes. Énoncé et corrigé de l'épreuve de mathématiques et informatique, concours d'entrée aux ENS de Cachan, Lyon et Ulm, session 2008. Revue de Mathématiques Spéciales, 119(1), 2008.



5. Hadda Cherroun, Alain Darte, and Paul Feautrier. Reservation Table Scheduling: Branch-and-Bound Based Optimization vs. Integer Linear Programming Techniques. RAIRO-OR, 41(4):427-454, December 2007. [doi:www.edpsciences.org/10.1051/ro:2007036]



6. Alain Darte and Guillaume Huard. New Complexity Results on Array Contraction and Related Problems. Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, 40(1):35-55, May 2005.



7. Alain Darte, Robert Schreiber, and Gilles Villard. Lattice-Based Memory Allocation. IEEE Transactions on Computers, 54(10):1242-1257, October 2005. Note: Special Issue, Tribute to B. Ramakrishna (Bob) Rau.



8. Daniel Chavarría-Miranda, Alain Darte, Robert Fowler, and John Mellor-Crummey. Generalized Multipartitioning of Multi-Dimensional Arrays for Parallelizing Line-Sweep Computations. Journal of Parallel and Distributed Computing, 63(9):887-911, 2003. Note: Special issue of best papers from IPDPS'02.



9. Alain Darte and Jean Mairesse. Énoncé et corrigé de l'épreuve de mathématiques et informatique, concours d'entrée aux ENS d'Ulm et Lyon, session 2002. Revue de Mathématiques Spéciales, 113(2):47-83, December 2002.



10. Alain Darte, Rob Schreiber, Bob Ramakrishna Rau, and Frédéric Vivien. Constructing and Exploiting Linear Schedules with Prescribed Parallelism. ACM Transactions on Design Automation of Electronic Systems, 7(1):159-172, 2002.



11. Alain Darte, Yves Robert, and Frédéric Vivien. Loop Parallelization Algorithms. In Santosh Pande, editor, Compiler Optimizations for Scalable Parallel Systems: Languages, Compilation Techniques, and Run Time Systems, volume 1808 of Lecture Notes in Computer Science, pages 141-172. Springer Verlag, 2001.



12. Alain Darte. On the Complexity of Loop Fusion. Parallel Computing, 26(9):1175-1193, July 2000.



13. Alain Darte and Guillaume Huard. Loop Shifting for Loop Compaction. International Journal of Parallel Programming, 28(5):499-534, 2000.



14. Alain Darte. Mathematical Tools for Loop Transformations: From Systems of Uniform Recurrence Equations to the Polytope Model. In M. H. Heath, A. Ranade, and R. S. Schreiber, editors, Algorithms for Parallel Processing, volume 105 of IMA Volumes in Mathematics and its Applications, pages 147-183. Springer Verlag, 1998.



15. Pierre Boulet, Alain Darte, Georges-André Silber, and Frédéric Vivien. Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation. Parallel Computing, 24(3):421-444, 1998.



16. Pierre-Yves Calland, Alain Darte, and Yves Robert. Circuit Retiming Applied to Decomposed Software Pipelining. IEEE Transactions on Parallel and Distributed Systems, 9(1):24-35, January 1998.



17. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. On the Removal of Anti and Output Dependences. International Journal of Parallel Programming, 26(3):285-312, 1998.



18. Alain Darte. Énoncé et corrigé de l'épreuve de mathématiques et informatique, concours d'entrée aux ENS de Cachan et Lyon, session 1997. Revue de Mathématiques Spéciales, 108(8):881-906, April 1998.



19. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms. Parallel Computing, 23(1):251-266, 1997.



20. Alain Darte, Georges-André Silber, and Frédéric Vivien. Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling. Parallel Processing Letters, 7(4):379-392, 1997.



21. Alain Darte and Frédéric Vivien. On the Optimality of Allen and Kennedy's Algorithm for Parallelism Detection in Nested Loops. Journal of Parallel Algorithms and Applications, 12(1-3):83-112, June 1997.



22. Alain Darte and Frédéric Vivien. Optimal Fine and Medium Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs. International Journal of Parallel Programming, 25(6):447-496, December 1997.



23. Alain Darte and Frédéric Vivien. Parallelizing Nested Loops with Approximation of Distance Vectors: A Survey. Parallel Processing Letters, 7(2):133-144, July 1997.



24. A. Darte, F. Desprez, J.-C. Mignot, and Y. Robert. TransTool: A Restructuring Tool for the Parallelization of Applications using High Performance Fortran. Journal of the Brazilian Computer Society, 3(2):5-15, 1996.



25. Alain Darte, Michèle Dion, and Yves Robert. A Characterization of One-to-One Modular Mappings. Parallel Processing Letters, 5(1):145-157, 1996.



26. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap. International Journal of Supercomputer Applications and High Performance Computing, 9(3):205-219, 1995.



27. Alain Darte and Yves Robert. Affine-by-Statement Scheduling of Uniform and Affine Loop Nests over Parametric Domains. Journal of Parallel and Distributed Computing, 29:43-59, 1995.



28. Alain Darte and Frédéric Vivien. Revisiting the Decomposition of Karp, Miller, and Winograd. Parallel Processing Letters, 5(4):551-562, 1995.



29. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. Integration, the VLSI journal, 17(1):33-51, 1994.



30. Alain Darte and Yves Robert. Constructive Methods for Scheduling Uniform Loop Nests. IEEE Transactions on Parallel and Distributed Systems, 5(8):814-822, 1994.



31. Alain Darte and Yves Robert. Mapping Uniform Loop Nests onto Distributed Memory Architectures. Parallel Computing, 20:679-710, 1994.



32. Alain Darte and Yves Robert. On the Alignment Problem. Parallel Processing Letters, 4(3):259-270, 1994.



33. A. Darte, T. Risset, and Y. Robert. Formal Methods for Solving the Algrebraic Path Problem. In L. Svensson F. Catthoor, editor, Application-Driven Architecture Synthesis, chapter 3, pages 47-69. Kluwer Academic Publishers, 1993.



34. Alain Darte. Regular Partitioning for Synthesizing Fixed-Size Systolic Arrays. INTEGRATION, The VLSI Journal, 12:293-304, December 1991.



35. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Nearly Optimal. Parallel Processing Letters, 1(2):73-81, 1991.

1. Alain Darte and Alexandre Isoard. Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes. In Björn Franke, editor, 24th International Conference on Compiler Construction (CC'15), Lecture Notes in Computer Science, London, UK, April 2015. Springer.



2. Alain Darte and Alexandre Isoard. Parametric Tiling with Inter-Tile Data Reuse. In Sanjay Rajopadhye and Sven Verdoolaege, editors, 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, January 2014.



3. Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Rank: A Tool to Check Program Termination and Computational Complexity. In International Workshop on Constraints in Software Testing Verification and Analysis (CSTVA'13), Luxembourg, pages 238, March 2013. [WWW]



4. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In Design, Automation & Test in Europe (DATE'13), Grenoble, France, pages 575-580, March 2013.



5. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), New Orleans, USA, pages 285-286, February 2012. IEEE Computer Society. Note: Short paper.



6. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. In 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), Paris, January 2012. Note: PPoPP'12 extended version.



7. Benoit Boissinot, Florian Brandner, Alain Darte, Benoit Dupont de Dinechin, and Fabrice Rastello. A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. In 9th Asian Symposium on Programming Languages and Systems (APLAS'11), pages 137-154, December 2011. Springer Verlag.



8. Florian Brandner and Alain Darte. Compiler-driven Optimization of the Worst-Case Execution Time. In Laure Gonnord and David Monniaux, editors, Workshop ``Analyse to Compile, Compile to Analyse'' (ACCA'11), held with CGO'11, Chamonix, April 2011.



9. Quentin Colombet, Florian Brandner, and Alain Darte. Studying Optimal Spilling in the Light of SSA. In International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, pages 25-34, October 2011. IEEE Computer Society.



10. Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs. In 17th International Static Analysis Symposium (SAS'10), Perpignan, France, pages 117-133, September 2010. ACM press.



11. Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-Level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool. In 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Rennes, France, pages 329-332, July 2010. IEEE Computer Society.



12. Florent Bouchez, Quentin Colombet, Alain Darte, Christophe Guillon, and Fabrice Rastello. Parallel Copy Motion. In 13th International Workshop on Software & Compilers for Embedded Systems (SCOPES'10), St. Goar, Germany, pages 1-10, June 2010. ACM Press.



13. Alain Darte. Understanding Loops: The Influence of the Decomposition of Karp, Miller, and Winograd. In 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'10), Grenoble, France, pages 139-148, July 2010. IEEE Computer Society. Note: Invited paper.



14. Benoit Boissinot, Alain Darte, Benoît Dupont de Dinechin, Christophe Guillon, and Fabrice Rastello. Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency. In International Symposium on Code Generation and Optimization (CGO'09), pages 114-125, March 2009. IEEE Computer Society Press. Note: Best paper award.



15. Florent Bouchez, Alain Darte, and Fabrice Rastello. Advanced Conservative and Optimistic Register Coalescing. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'08), Atlanta, GA, USA, pages 147-156, October 2008. ACM Press.



16. Christophe Alias, Fabrice Baray, and Alain Darte. Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 73-82, June 2007. ACM Press.



17. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Register Coalescing. In International Symposium on Code Generation and Optimization (CGO'07), pages 102-114, March 2007. IEEE Computer Society Press. Note: Best paper award.



18. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Spill Everywhere under SSA Form. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 103-112, June 2007. ACM Press.



19. Alain Darte and Clément Quinson. Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. In The 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'07), pages 554-561, July 2007. IEEE Computer Society.



20. Florent Bouchez, Alain Darte, Christophe Guillon, and Fabrice Rastello. Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove?. In Annual Workshop in Duplicating, Deconstructing, and Debunking (WDDD'06), held in conjunction with the International Symposium on Computer Architecture (ISCA'33), Boston, MA, USA, July 2006.



21. Florent Bouchez, Alain Darte, Christophe Guillon, and Fabrice Rastello. Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How. In International Workshop on Languages and Compilers for Parallel Computing (LCPC'06), New Orleans, FL, USA, November 2006. Springer Verlag.



22. Hadda Cherroun, Alain Darte, and Paul Feautrier. Scheduling under Resource Constraints using Dis-Equalities. In Design Automation and Test in Europe (DATE'06), March 2006.



23. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. In IEEE International Conference on Application-Specific Systems, Architecture, and Processors (ASAP'05), pages 28-35, 2005. IEEE Computer Society Press.



24. Alain Darte and Robert Schreiber. A Linear-Time Algorithm for Optimal Barrier Placement. In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'05), Chicago, IL, USA, pages 26-35, June 2005.



25. A. Darte, R. Schreiber, and G. Villard. Lattice-Based Memory Allocation. In 6th ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES'03), San Jose, CA, USA, pages 298-308, October 2003.



26. Daniel Chavarría-Miranda, Alain Darte, Robert Fowler, and John Mellor-Crummey. Generalized Multipartitioning for Multi-Dimensional Arrays. In 16th International Parallel and Distributed Processing Symposium (IPDPS'02), Fort Lauderdale, Florida, April 2002. IEEE Computer Society Press. Note: « Best paper award ».



27. A. Darte and G. Huard. Complexity of Multi-Dimensional Loop Alignment. In 19th International Symposium on Theoretical Aspects of Computer Science (STACS'02), volume 2285, pages 179-191, March 2002. Springer Verlag.



28. A. Darte and G. Huard. New Results on Array Contraction. In 13th International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pages 359-370, July 2002. IEEE Computer Society Press.



29. A. Darte, C. Diderich, M. Gengler, and F. Vivien. Scheduling the Computations of a Loop Nest with Respect to a Given Mapping. In European Conference on Parallel Computing (Euro-Par'00), volume 1900 of LNCS, München, Germany, pages 405-414, August 2000. Springer Verlag.



30. A. Darte, R. Schreiber, B. R. Rau, and F. Vivien. A Constructive Solution to the Juggling Problem in Systolic Array Synthesis. In International Parallel and Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, pages 815-821, May 2000.



31. A. Darte and G.-A. Silber. Temporary Arrays for Distribution of Loops with Control Dependences. In European Conference on Parallel Computing (Euro-Par'00), volume 1900 of LNCS, München, Germany, pages 357-367, August 2000. Springer Verlag.



32. Alain Darte. On the Complexity of Loop Fusion. In International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pages 149-157, October 1999.



33. Alain Darte and Guillaume Huard. Loop Shifting for Loop Compaction. In Languages and Compilers for Parallel Computing (LCPC'99), volume 1863 of Lecture Notes in Computer Science, pages 415-431, August 1999. Springer Verlag.



34. Georges-André Silber and Alain Darte. The Nestor Library: A Tool for Implementing Fortran Source to Source Transformations. In High Performance Computing and Networking (HPCN'99), volume 1593 of Lecture Notes in Computer Science, pages 653-662, April 1999. Springer Verlag.



35. T. Brandes, S. Chaumette, M.-C. Counilh, A. Darte, F. Desprez, J.C Mignot, and J. Roman. HPFIT and the TransTool Environment. In J. J. Dongarra and B. Tourancheau, editors, 3rd Workshop on Environments and Tools for Parallel Scientific Computing, August 1996. SIAM Press.



36. Pierre-Yves Calland, Alain Darte, and Yves Robert. A New Guaranteed Heuristic for the Software Pipelining Problem. In 1996 International Conference on Supercomputing (ICS'96), pages 261-269, 1996. ACM Press.



37. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. On the Removal of Anti and Output Dependences. In J. Fortes, C. Mongenet, K. Parhi, and V. Taylor, editors, Application Specific Systems, Architectures and Processors (ASAP'96), pages 353-364, 1996. IEEE Computer Science Press.



38. P.-Y. Calland, A. Darte, Y. Robert, and F. Vivien. Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms. In J. J. Dongarra and B. Tourancheau, editors, 3rd Workshop on Environments and Tools for Parallel Scientific Computing, August 1996. SIAM Press.



39. Alain Darte and Frédéric Vivien. On the Optimality of Allen and Kennedy's Algorithm for Parallelism Detection in Nested Loops. In Europar'96, volume 1123 of Lecture Notes in Computer Science, pages 379-388, August 1996. Springer Verlag.



40. Alain Darte and Frédéric Vivien. Optimal Fine and Medium Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs. In Parallel and Architectures and Compilation Techniques (PACT'96), pages 281-291, October 1996. IEEE Computer Society Press.



41. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Heuristics for the Evaluation of Array Expressions on State-of-the-Art Massively Parallel Machines. In M. Moonen and F. Catthoor, editors, Algorithms and Parallel VLSI Architectures III, pages 319-330, 1995. North Holland.



42. Alain Darte, Michèle Dion, and Yves Robert. A Characterization of One-to-One Modular Mappings. In 7th IEEE Symposium on Parallel and Distributed Processing (SPDP'95), pages 382-389, 1995. IEEE Computer Science Press.



43. Alain Darte and Frédéric Vivien. A Classification of Nested Loops Parallelization Algorithms. In INRIA-IEEE Symposium on Emerging Technologies and Factory Automation (ETFA'95), pages 217-224, 1995. IEEE Computer Society Press.



44. Alain Darte and Frédéric Vivien. Revisiting the Decomposition of Karp, Miller and Winograd. In Application Specific Array Processors (ASAP'95), pages 13-25, 1995. IEEE Computer Society Press.



45. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap. In B. Buchberger and J. Volkert, editors, Parallel Processing: CONPAR 94-VAPP VI, volume 854 of Lecture Notes in Computer Science, pages 713-724, 1994. Springer Verlag.



46. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. In Scalable High Performance Computing Conference (SHPCC'94), pages 568-576, 1994. IEEE Computer Society Press.



47. Alain Darte. Mapping Uniform Loop Nests onto Distributed Memory Architectures. In G. R. Joubert, D. Trystram, F. J. Peters, and D. J. Evans, editors, Parallel Computing: Trends and Applications, pages 287-294, 1994. Elsevier Science B.V..



48. Alain Darte and Yves Robert. The Alignment Problem for Perfect Uniform Loop Nest: NP-Completeness and Heuristics. In J. J. Dongarra and B. Tourancheau, editors, 2nd Workshop on Environments and Tools for Parallel Scientific Computing, pages 33-42, 1994. SIAM Press.



49. A. Darte, T. Risset, and Y. Robert. Loop Nest Scheduling and Transformations. In J.J. Dongarra et al., editor, Environments and Tools for Parallel Scientific Computing, volume 6 of Advances in Parallel Computing, pages 309-332, 1993. North-Holland.



50. Alain Darte and Yves Robert. Communication-Minimal Mapping of Uniform Loop Nests onto Distributed Memory Architectures. In L. Dadda and B. Wah, editors, Application Specific Array Processors (ASAP'93), pages 1-14, 1993. IEEE Computer Society Press.



51. Alain Darte. Two Heuristics for Task Scheduling. In Patrice Quinton and Yves Robert, editors, Algorithms and Parallel VLSI Architectures, volume 2, pages 383-388, 1992. Elsevier Science Publishers B.V..



52. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Close to Optimality. In J. A. B. Fortes, E. Lee, and T. Meng, editors, Application Specific Array Processors (ASAP'92), pages 37-46, 1992. IEEE Computer Society Press.



53. Alain Darte and Yves Robert. Scheduling Uniform Loop Nests. In R. Melhem, editor, ISMM Conference on Parallel and Distributed Systems, pages 75-82, 1992. ISMM Press.



54. Alain Darte and Yves Robert. Séquencement des nids de boucles. In Michel Cosnard, Maurice Nivat, and Yves Robert, editors, Algorithmique Parallèle, pages 343-368, 1992. Masson.



55. A. Darte, T. Risset, and Y Robert. Synthesizing Systolic Arrays: Some Recent Developments. In M. Valero et al., editor, Application Specific Array Processors, pages 372-386, 1991. IEEE Computer Society Press.



56. A. Darte, Y. Robert, and T. Risset. Systolic Systems. In P.J. Hargraven, editor, 2nd IEE International Specialist Seminar on Parallel Digital Processors, volume 334 of IEEE Conference Publication, pages 6-10, 1991. IEEE Press.

1. Christophe Alias, Alain Darte, and Alexandru Plesco. Kernel Offloading with Optimized Remote Accesses. Research Report RR-7697, INRIA, July 2011. [WWW]



2. Christophe Alias, Alain Darte, and Alexandru Plesco. Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis. Research Report RR-7648, INRIA, June 2011. [WWW]



3. Florian Brandner, Benoit Boissinot, Alain Darte, Benoît Dupont de Dinechin, and Fabrice Rastello. Computing Liveness Sets for SSA-Form Programs. Research Report RR-7503, INRIA, April 2011. [WWW]



4. Benoit Boissinot, Philip Brisk, Alain Darte, and Fabrice Rastello. SSI Revisited. Technical report RR2009-24, LIP, July 2009. [WWW]



5. Christophe Alias, Fabrice Baray, and Alain Darte. Lattice-Based Array Contraction: from Theory to Practice. Research Report 2007-44, INRIA, November 2007.



6. Florent Bouchez, Alain Darte, and Fabrice Rastello. Improvements to Conservative and Optimistic Register Coalescing. Technical report RR2007-41, LIP, ENS-Lyon, France, March 2007. [WWW]



7. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Spill Everywhere under SSA Form. Technical report RR2007-42, LIP, ENS-Lyon, France, March 2007. [WWW]



8. Florent Bouchez, Alain Darte, and Fabrice Rastello. On the Complexity of Register Coalescing. Technical report RR2006-15, LIP, ENS-Lyon, France, March 2006. [WWW]



9. Florent Bouchez, Alain Darte, and Fabrice Rastello. Register Allocation: What does Chaitin's NP-Completeness Proof Really Prove?. Technical report RR2006-13, LIP, ENS-Lyon, France, March 2006. [WWW]



10. Florent Bouchez, Alain Darte, Christophe Guillon, and Fabrice Rastello. Register Allocation and Spill Complexity under SSA. Technical report RR2005-33, LIP, ENS Lyon, France, August 2005. [WWW]



11. Hadda Cherroun, Alain Darte, and Paul Feautrier. Scheduling with Resource Constraints using Dis-Equations. Technical report 2005-40, LIP, ENS-Lyon, September 2005.



12. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. Technical report 2005-15, LIP, ENS-Lyon, April 2005.



13. Alain Darte and Rob Schreiber. Nested Circular Arc Families: A Model for Barrier Placement in Single-Program, Multiple-Data Codes with Nested Loops. Technical report RR2004-57, LIP, ENS-Lyon, December 2004.



14. Alain Darte, Rob Schreiber, and Gilles Villard. Lattice-Based Memory Allocation. Technical report RR2004-23, LIP, ENS-Lyon, April 2004.



15. Alain Darte and Guillaume Huard. New Complexity Results on Array Contraction and Related Problems. Technical report RR2002-41, LIP, ENS-Lyon, France, October 2002.



16. Alain Darte and Guillaume Huard. New Results on Array Contraction. Technical report RR2002-17, LIP, ENS-Lyon, France, April 2002.



17. Daniel Chavarría-Miranda, Alain Darte, Robert Fowler, and John Mellor-Crummey. Efficient Parallelization of Line-Sweep Computations. Technical report RR2001-45, LIP, ENS-Lyon, France, November 2001.



18. Alain Darte and Guillaume Huard. Loop Shifting for Loop Parallelization. Technical report RR2000-22, LIP, ENS-Lyon, France, May 2000.



19. Alain Darte and Guillaume Huard. Loop Shifting for Loop Compaction. Technical report RR1999-29, LIP, ENS-Lyon, France, May 1999.



20. Alain Darte and Rob Schreiber. A Constructive Solution to the Juggling Problem in Systolic Array Synthesis. Technical report RR1999-15, LIP, ENS-Lyon, France, February 1999.



21. Alain Darte. On the Complexity of Loop Fusion. Technical report RR1998-50, LIP, ENS-Lyon, France, October 1998.



22. Alain Darte and Georges-André Silber. The Nestor Library: A Tool for Implementing Fortran Source to Source Transformations. Technical report RR1998-42, LIP, ENS-Lyon, France, September 1998.



23. Pierre Boulet, Alain Darte, Georges-André Silber, and Frédéric Vivien. Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation. Technical report RR97-17, LIP, ENS-Lyon, France, June 1997.



24. Alain Darte. Mathematical Tools for Loop Transformations: From Systems of Uniform Recurrence Equations to the Polytope Model. Technical report RR97-26, LIP, ENS-Lyon, France, September 1997.



25. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. On the Removal of Anti and Output Dependences. Technical report RR96-04, LIP, ENS-Lyon, France, February 1996.



26. Pierre-Yves Calland, Alain Darte, Yves Robert, and Frédéric Vivien. Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms. Technical report RR96-13, LIP, ENS-Lyon, France, June 1996.



27. A. Darte, F. Desprez, J.-C. Mignot, T. Brandes, S. Chaumette, M.-C. Counilh, and J. Roman. A Set of Integrated Tools for the Parallelization of Applications Using High Performance Fortran. Technical report RR96-28, LIP, ENS-Lyon, France, September 1996.



28. Alain Darte, Georges-André Silber, and Frédéric Vivien. Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling. Technical report RR96-34, LIP, ENS-Lyon, France, November 1996.



29. Alain Darte and Frédéric Vivien. On the Optimality of Allen and Kennedy's Algorithm for Parallelism Detection in Nested Loops. Technical report RR96-05, LIP, ENS-Lyon, France, February 1996.



30. Alain Darte and Frédéric Vivien. Optimal Fine and Medium-Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs. Technical report RR96-06, LIP, ENS-Lyon, France, April 1996.



31. Pierre-Yves Calland, Alain Darte, and Yves Robert. A New Guaranteed Heuristic for the Software Pipelining Problem. Technical report RR95-42, LIP, ENS-Lyon, France, November 1995.



32. Alain Darte, Michèle Dion, and Yves Robert. A Characterization of One-to-One Modular Mappings. Technical report RR95-09, LIP, ENS-Lyon, France, April 1995.



33. Alain Darte and Frédéric Vivien. A Comparison of Nested Loops Parallelization Algorithms. Technical report RR95-11, LIP, ENS-Lyon, France, May 1995.



34. Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap. Technical report RR94-10, LIP, ENS-Lyon, France, March 1994.



35. Alain Darte and Frédéric Vivien. Automatic Parallelization Based on Multi-Dimensional Scheduling. Technical report RR94-24, LIP, ENS-Lyon, France, September 1994.



36. Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-Ultimate Tiling?. Technical report RR93-36, LIP, ENS-Lyon, November 1993.



37. Alain Darte and Yves Robert. A Graph-Theoretic Approach to the Alignment Problem. Technical report RR93-20, LIP, ENS-Lyon, France, July 1993.



38. Alain Darte and Yves Robert. Mapping Uniform Loop Nests onto Distributed Memory Architectures. Technical report RR93-03, LIP, ENS-Lyon, France, January 1993.



39. Alain Darte. Affine-by-Statement Scheduling: Extensions for Affine Dependences and Several Parameters. Technical report RT92-03, LIP, ENS-Lyon, France, May 1992.



40. Alain Darte and Yves Robert. Affine-by-Statement Scheduling of Uniform Loop Nests over Parametric Domains. Technical report RR92-16, LIP, ENS-Lyon, France, April 1992.



41. Alain Darte and Yves Robert. Scheduling Uniform Loop Nests. Technical report RR92-10, LIP, ENS-Lyon, France, February 1992.



42. Alain Darte. Regular Partitioning for Synthesizing Fixed-Size Systolic Arrays. Technical report RR91-10, LIP, ENS-Lyon, France, 1991.



43. Alain Darte. Two Heuristics for Task Scheduling. Technical report RR91-30, LIP, ENS-Lyon, France, 1991.



44. Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Nearly Optimal. Technical report RR91-35, LIP, ENS-Lyon, France, 1991.



45. Alain Darte, Tanguy Risset, and Yves Robert. Synthesizing Systolic Arrays: Some Recent Developments. Technical report RR91-09, LIP, ENS-Lyon, France, 1991.



46. Alain Darte and Jean-Marc Delosme. Partitioning for Array Processors. Technical report RR90-23, LIP, ENS-Lyon, France, 1990.

1. Alain Darte and Rob Schreiber. System and Method of Optimizing Memory Usage with Data Lifetimes. US patent number 7363459, April 2008.



2. Alain Darte, Bantwal Ramakrishna Rau, and Rob Scheiber. Programmatic Iteration Scheduling for Parallel Processors. US patent number 6438747, August 2002.



3. Alain Darte and Rob Schreiber. Programmatic Method For Reducing Cost of Control In Parallel Processes. US patent number 6374403, April 2002.

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