Publications

CASH publications on Hal

 

Journal articles12 documents

  • Christophe Alias, Alexandru Plesco. Optimizing Affine Control with Semantic Factorizations. ACM Transactions on Architecture and Code Optimization (TACO) , ACM, 2017, 14 (4), pp.27. 〈http://taco.acm.org/〉. 〈hal-01470873v3〉
  • Maroua Maalej, Vitor Paisante, Fernando Magno Quintao Pereira, Laure Gonnord. Combining Range and Inequality Information for Pointer Disambiguation. Science of Computer Programming, Elsevier, 2017. 〈hal-01625402〉
  • Matthieu Moy, Claude Helmstetter, Tayeb Bouhadiba, Florence Maraninchi. Modeling Power Consumption and Temperature in TLM Models. Leibniz Transactions on Embedded Systems, European Design and Automation Association (EDAA) \ EMbedded Systems Special Interest Group (EMSIG) and Schloss Dagstuhl — Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing., 2016, 3 (1), pp.03:1-03:29. 〈10.4230/LITES-v003-i001-a003〉. 〈hal-01339441〉
  • Denis Becker, Matthieu Moy, Jérôme Cornet. Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study. Electronics, MDPI, 2016, 5 (2), pp.22. 〈10.3390/electronics5020022〉. 〈hal-01321055〉
  • Karine Altisen, Matthieu Moy. Causality problem in real-time calculus. Formal Methods in System Design, Springer Verlag, 2016, 48, pp.1 – 45. 〈10.1007/s10703-016-0250-y〉. 〈hal-01406162〉
  • Matthieu Moy. Compte-rendu d’habilitation : Modélisation à haut niveau d’abstraction pour les systèmes embarqués. Technique et Science Informatiques, Hermès-Lavoisier, 2014, 33 (3), pp.285-293. 〈hal-00986536〉
  • Laure Gonnord, Peter Schrammel. Abstract Acceleration in Linear Relation Analysis. Science of Computer Programming, Elsevier, 2014, 93, part B (125 – 153), pp.125 – 153. 〈10.1016/j.scico.2013.09.016〉. 〈hal-00876627〉
  • Paul Feautrier, Abdoulaye Gamatié, Laure Gonnord. Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction. CSI Journal of Computing, Computer Society of India, 2012, 1 (4), pp.8:86–8:99. 〈hal-00860785〉
  • Christophe Alias, Bogdan Pasca, Alexandru Plesco. FPGA-Specific Synthesis of Loop Nests with Pipelined Computational Cores. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2012, 36 (8), pp.606-619. 〈10.1016/j.micpro.2012.06.009〉. 〈hal-00761515〉
  • Laure Gonnord, Jean-Philippe Babau. Qinna: a component-based framework for runtime safe resource adaptation of embedded systems. Scalable Computing : Practice and Experience, West University of Timisoara, 2009, 10 (3), pp.253-264. 〈hal-00670185〉
  • Nicolas Halbwachs, David Merchat, Laure Gonnord. Some ways to reduce the space dimension in polyhedra computations. Formal Methods in System Design, Springer Verlag, 2006, 29 (1), pp.79-95. 〈10.1007/s10703-006-0013-2〉. 〈hal-00189633〉
  • Matthieu Moy, Florence Maraninchi, Laurent Maillet-Contoz. LusSy: an Open Tool for the Analysis of Systems-on-a-Chip at the Transaction Level. Design Automation for Embedded Systems, Springer Verlag, 2005, 10 (32), pp.73-104. 〈10.1007/s10617-006-9044-6〉. 〈hal-00310999〉

 

Conference papers54 documents

  • Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Parallel Code Generation of Synchronous Programs for a Many-core Architecture. Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. 2018, 〈https://www.date-conference.com/〉. 〈hal-01667594v2〉
  • Laure Gonnord, Sébastien Mosser. Du code aux modèles, des modèles au code: enseigner les langages dédiés (DSL). Conférence en Ingénierie du Logiciel, Jun 2018, Grenoble, France. 〈hal-01816239〉
  • Christophe Alias, Alexandru Plesco. Improving Communication Patterns in Polyhedral Process Networks. HIP3ES 2018 – Sixth International Workshop on High Performance Energy Efficient Embedded Systems, Jan 2018, Manchester, United Kingdom. 〈hal-01725143〉
  • Maroua Maalej, Vitor Paisante, Ramos Pedro, Laure Gonnord, Fernando Pereira. Pointer Disambiguation via Strict Inequalities. Code Generation and Optimisation , Feb 2017, Austin, United States. Proceedings of the 2017 International Symposium on Code Generation and Optimization, pp.134-147, 2017. 〈hal-01387031〉
  • Hamza Rihani, Claire Maiza, Matthieu Moy. Efficient Execution of Dependent Tasks on Many-Core Processors. RTSOPS, Jul 2016, Toulouse, France. 〈hal-01406057〉
  • Hamza Rihani, Matthieu Moy, Claire Maiza, Robert Davis, Sebastian Altmeyer. Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor. RTNS, Nov 2016, Brest, France. 〈hal-01406145〉
  • Denis Becker, Matthieu Moy, Jérôme Cornet. SycView: Visualize and Profile SystemC Simulations. 3rd Workshop on Design Automation for Understanding Hardware Designs, DUHDe 2016 , Mar 2016, Dresden, Germany. 〈hal-01295282〉
  • Christophe Alias, Carsten Fuhs, Laure Gonnord. Estimation of Parallel Complexity with Rewriting Techniques. Workshop on Termination, Sep 2016, Obergurgl, Austria. Workshop on Termination, 2016, Workshop on Termination. 〈http://cl-informatik.uibk.ac.at/events/wst-2016/〉. 〈hal-01345914〉
  • David Monniaux, Laure Gonnord. Cell morphing: from array programs to array-free Horn clauses. Xavier Rival. 23rd Static Analysis Symposium (SAS 2016), Sep 2016, Edimbourg, United Kingdom. Static Analysis Symposium, Static Analysis Symposium. 〈http://staticanalysis.org/sas2016〉. 〈hal-01206882v3〉
  • Vitor Paisante, Maroua Maalej, Leonardo Barbosa, Laure Gonnord, Fernando Magno Quintão Pereira. Symbolic Range Analysis of Pointers. International Symposium of Code Generation and Optmization, Mar 2016, Barcelona, Spain. Proceedings of CGO’16, pp.791-809, 2016, Code Generation and Optimization. 〈hal-01228928〉
  • Denis Becker, Matthieu Moy, Jérôme Cornet. Challenges for the Parallelization of Loosely Timed SystemC Programs. IEEE International Symposium on Rapid System Prototyping, Oct 2015, Amsterdam, Netherlands. 〈hal-01214891〉
  • Hamza Rihani, Matthieu Moy, Claire Maiza, Sebastian Altmeyer. WCET analysis in shared resources real-time systems with TDMA buses. RTNS 2015, Nov 2015, Lille, France. RTNS: 23rd International Conference on Real-Time Networks and Systems, 2015, 23rd International Conference on Real-Time Networks and Systems. 〈http://rtns2015.lifl.fr/〉. 〈10.1145/2834848.2834871〉. 〈hal-01243244〉
  • Laure Gonnord, David Monniaux, Gabriel Radanne. Synthesis of ranking functions using extremal counterexamples. Programming Languages, Design and Implementation, Jun 2015, Portland, Oregon, United States. 〈10.1145/2737924.2737976〉. 〈hal-01144622〉
  • Raphael Ernani Rodrigues, Péricles Alves, Fernando Pereira, Laure Gonnord. Real-World Loops are Easy to Predict: A Case Study. Workshop on Software Termination (WST’14), Jul 2014, Vienne, Austria. 2014. 〈hal-01006208〉
  • Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, Yun Zou. CART: Constant Aspect Ratio Tiling. 4th International Workshop on Polyhedral Compilation Techniques (IMPACT’14), Jan 2014, Vienna, Austria. 2014. 〈hal-00915827〉
  • Henrique Nazaré, Izabela Maffra, Willer Santos, Leonardo Oliveira, Fernando Magno Quintão Pereira, et al.. Validation of Memory Accesses Through Symbolic Analyses. ACM International Conference on Object Oriented Programming Systems Languages & Applications (OOPSLA’14), Oct 2014, Portland, Oregon, United States. pp.791-809, 2014, 〈10.1145/2660193.2660205〉. 〈hal-01006209〉
  • Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal Vivet. Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications. Design, Automation and Test in Europe (DATE), Mar 2013, Grenoble, France. pp.1185, 2013. 〈hal-00807046〉
  • Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi. System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management. Design, Automation, and Test in Europe (DATE), Mar 2013, Grenoble, France. pp.1609, 2013. 〈hal-00807048〉
  • Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi, Jérôme Cornet, Laurent Maillet-Contoz, et al.. Co-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers. Virtual Prototyping of Parallel and Embedded Systems (VIPES), May 2013, Boston, United States. 2013. 〈hal-00807354〉
  • Matthieu Moy. Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach. DATE, Mar 2013, Grenoble, France. pp.9, 2013. 〈hal-00761047〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. Design, Automation, and Test in Europe (DATE’13), Mar 2013, Grenoble, France. 2013. 〈hal-00761533〉
  • Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord. Rank: a tool to check program termination and computational complexity. Constraints in Software Testing Verification and Analysis, Mar 2013, Luxembourg. 〈hal-00801571〉
  • Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias. Semantic Tiling. Workshop on Leveraging Abstractions and Semantics in High-performance Computing (LASH-C’13), Aug 2013, Shenzhen, China. 〈hal-01664051〉
  • Jérôme Cornet, Laurent Maillet-Contoz, Ilija Materic, Sylvian Kaiser, Hela Boussetta, et al.. Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top Box. DAC, Jun 2012, San Francisco, United States. pp.SESSION 10U: USER TRACK, 2012. 〈hal-00716051〉
  • Julien Henry, David Monniaux, Matthieu Moy. Succinct Representations for Abstract Interpretation. Static analysis symposium (SAS), Sep 2012, Deauville, France. Springer, pp.283-299, 2012, Lecture notes in Computer Science. 〈10.1007/978-3-642-33125-1_20〉. 〈hal-00709833〉
  • Julien Henry, David Monniaux, Matthieu Moy. PAGAI: a path sensitive static analyzer. Tools for Automatic Program AnalysiS (TAPAS 2012), Sep 2012, Deauville, France. pp.3, 2012. 〈hal-00718438〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT’12), held with HIPEAC’12, Jan 2012, Paris, France. 2012. 〈hal-00761477〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP’12), Feb 2012, New Orleans, United States. IEEE Computer Society, pp.285–286, 2012, 〈10.1145/2145816.2145856〉. 〈hal-00761473〉
  • Guillaume Andrieu, Christophe Alias, Laure Gonnord. SToP : Scalable Termination analysis of (C) Programs (tool presentation). Tapas 2012, Sep 2012, Deauville, France. 2012. 〈hal-00760926〉
  • Matthieu Moy. Efficient and Playful Tools to Teach Unix to New Students. ITiCSE, Jun 2011, Darmstadt, Germany. pp.0, 2011. 〈hal-00574783〉
  • Abdoulaye Gamatié, Laure Gonnord. Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems. ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2011, Apr 2011, Chicago, IL, United States. pp.71-80, 2011, 〈10.1145/1967677.1967688〉. 〈inria-00586137〉
  • Giovanni Funchal, Matthieu Moy. Modeling of Time in Discrete-Event Simulation of Systems-on-Chip. MEMOCODE, Jul 2011, Cambridge, United Kingdom. 2011. 〈hal-00595637〉
  • David Monniaux, Laure Gonnord. Using Bounded Model Checking to Focus Fixpoint Iterations. Eran Yahav. Static analysis symposium (SAS), Sep 2011, Venezia, Italy. Springer, 6887, pp.369-385, 2011, Lecture notes in Computer Science. 〈10.1007/978-3-642-23702-7_27〉. 〈hal-00600087〉
  • Kevin Marquet, Matthieu Moy, Bertrand Jeannet. Efficient Encoding of SystemC/TLM in Promela. DATICS-IMECS, Mar 2011, Hong Kong SAR China. 2011. 〈hal-00557515〉
  • Giovanni Funchal, Matthieu Moy, Florence Maraninchi, Laurent Maillet-Contoz. Faithfulness Considerations for Virtual Prototyping of Systems-on-Chip. 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2011, Greece. 2011. 〈hal-00559986〉
  • Benoit Combemale, Laure Gonnord, Vlad Rusu. A Generic Tool for Tracing Executions Back to a DSML’s Operational Semantics. Seventh European Conference on Modelling Foundations and Applications, Jun 2011, Birmingham, United Kingdom. Springer Verlag, 6698, pp.35-51, 2011, Lecture Notes in Computer Science. 〈hal-00593425〉
  • Karine Altisen, Matthieu Moy. Causality closure for a new class of curves in real-time calculus. Proceedings of the 1st International Workshop on Worst-Case Traversal Time, Nov 2011, Vienna, Austria. ACM, pp.3–10, 2011, 〈10.1145/2071589.2071590〉. 〈hal-00648628〉
  • Christophe Alias, Bogdan Pasca, Alexandru Plesco. Automatic Generation of FPGA-Specific Pipelined Accelerators. International Symposium on Applied Reconfigurable Computing (ARC’11), Mar 2011, Belfast, United Kingdom. LNCS 6578, Springer, 2011, 〈http://www.springer.com/fr/book/9783642194740〉. 〈ensl-00549682〉
  • Kevin Marquet, Matthieu Moy. PinaVM: a SystemC Front-End Based on an Executable Intermediate Representation. International Conference on Embedded Software, Oct 2010, Scottsdale, United States. pp.79, 2010. 〈hal-00495874〉
  • Matthieu Moy, Karine Altisen. Arrival Curves for Real-Time Calculus: the Causality Problem and its Solutions. Javier Esparza and Rupak Majumdar. Tools and Algorithms for the Construction and Analysis of Systems, Mar 2010, Paphos, Cyprus. Springer, pp.358, 2010, LNCS. 〈hal-00442257〉
  • Karine Altisen, Yanhong Lui, Matthieu Moy. Performance Evaluation of Components Using a Granularity-based Interface Between Real-Time Calculus and Timed Automata. 8th Workshop on Quantitative Aspects of Programming Languages, Mar 2010, Paphos, Cyprus. pp.166, 2010, 〈10.4204/EPTCS〉. 〈hal-00450292〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators : An Experience With the Altera C2H HLS Tool. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’10), Jul 2010, Rennes, France. 〈hal-01664033〉
  • Paul Feautrier, Laure Gonnord. Accelerated Invariant Generation for C Programs with Aspic and C2fsm. Tools for Automatic Program AnalysiS, Sep 2010, Perpignan, France. 2010, 〈10.1016/j.entcs.2010.09.014〉. 〈inria-00523320〉
  • Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord. Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs. Static Analysis Symposium, Sep 2010, Perpignan, France. 2010, 〈10.1007/978-3-642-15769-1〉. 〈inria-00523298〉
  • Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, et al.. Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT’09), Sep 2009, Raleigh, United States. 〈ensl-01664020〉
  • Laure Gonnord, Jean-Philippe Babau. Quantity of Resource Properties Expression and Runtime Assurance for Embedded Systems. AICCSA – The seventh ACS/IEEE International Conference on Computer Systems and Applications, May 2009, Rabat, Morocco. IEEE, 2009. 〈inria-00349918v2〉
  • Jean-Philippe Babau, Laure Gonnord. Runtime resource assurance and adaptation with Qinna framework : a case study. Real Time Software (RTS) 2008, Oct 2008, Poland. pp.617-624, 2008, 〈10.1109/IMCSIT.2008.4747307〉. 〈hal-00801546〉
  • Florence Maraninchi, Matthieu Moy, Jérôme Cornet, Laurent Maillet-Contoz, Claude Helmstetter, et al.. SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation. IEEE. 2008 Joint IEEE-NEWCAS and TAISA Conference, Jun 2008, Montréal, Canada. 2008. 〈hal-00311011〉
  • Laure Gonnord, Nicolas Halbwachs. Combining Widening and Acceleration in Linear Relation Analysis. Static Analysis (SAS 2006), Aug 2006, Seoul, South Korea. pp.144-160, 2006, 〈10.1007/11823230_10〉. 〈hal-00189614〉
  • Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, Matthieu Moy. Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip. IEEE. Formal Methods in Computer Aided Design (FMCAD’06), Nov 2006, San Jose, United States. pp.171-178, 2006, 〈10.1109/FMCAD.2006.10〉. 〈hal-00311006〉
  • Matthieu Moy, Florence Maraninchi, Laurent Maillet-Contoz. Pinapa: An extraction tool for systemc descriptions of systems-on-a-chip. ACM international conference on Embedded software, Jun 2005, New-York, United States. pp.317 – 324, 2005, 〈10.1145/1086228.1086286〉. 〈hal-00198669〉
  • Matthieu Moy, Florence Maraninchi, Laurent Maillet-Contoz. LusSy: A toolbox for the analysis of systems-on-a-chip at the transactional level. International Conference on Application of Concurrency to System Design (ACSD), Jun 2005, Saint-Malo, France. ISBN ~ ISSN:1550-4808 0-7695-2363-3, pp.26 – 35, 2005, 〈10.1109/ACSD.2005.23〉. 〈hal-00198681〉
  • Christophe Alias. TeMa : an Efficient Tool to find High-Performance Library Patterns in Source Code. International Workshop on Patterns in High-Performance Computing (PatHPC’05), May 2005, Urbana Champaign, United States. 〈ensl-01663997〉
  • Christophe Alias, Denis Barthou. On Domain Specific Language Re-Engineering. Sep 2005, ACM, 2005. 〈hal-00141073〉
  • Christophe Alias, Denis Barthou. Deciding Where to Call Performance Libraries. Aug 2005, IEEE, 2005. 〈hal-00141074〉
  • Laure Gonnord, Nicolas Halbwachs, Pascal Raymond. From Discrete Duration Calculus to Symbolic Automata. Third International Workshop on Synchronous Languages, Applications, and Programs (SLAP 2004), Mar 2003, Barcelona, Spain. 153 (4), pp.3-18, 2006, 〈10.1016/j.entcs.2006.02.022〉. 〈hal-00198433〉

 

Book sections1 document

  • Matthieu Moy. Chapter “Formal Verification”. Frank Ghenassia. Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems, Springer, 15 p., 2005, ISBN: 0-387-26232-6. 〈hal-00311014〉

 

Patents1 document

  • Christophe Alias, Alexandru Plesco. Procédé de synthèse de circuits, dispositif et programme d’ordinateur associés. France, N° de brevet: FR1453308. 2014. 〈hal-01096129〉

 

Preprints, Working Papers, …3 documents

  • Kevin Marquet, Matthieu Moy, Bageshri Karkare. A Theoretical and Experimental Review of SystemC Front-ends. 2010. 〈hal-00495886〉
  • Karine Altisen, Matthieu Moy. ac2lus: Bringing SMT-solving and Abstract Interpretation Techniques to Real-Time Calculus through the Synchronous Language Lustre. 2010. 〈hal-00475745〉
  • Claus Traulsen, Jérôme Cornet, Matthieu Moy, Florence Maraninchi. A SystemC/TLM semantics in Promela and its Possible Applications. 2007. 〈hal-00294143〉

 

Reports23 documents

  • Laure Gonnord, Paul Iannetta, Lionel Morel. Semantic Polyhedral Model for Arrays and Lists. [Research Report] RR-9183, Inria Grenoble Rhône-Alpes; UCBL; LIP – ENS Lyon; CEA List. 2018. 〈hal-01815759〉
  • Christophe Alias. FIFO Recovery by Depth-Partitioning is Complete on Data-aware Process Networks. [Research Report] RR-9187, INRIA Grenoble – Rhone-Alpes. 2018. 〈hal-01818585〉
  • Laure Gonnord, Szabolcs-Marton Bagoly, Lionel Morel. Static Analysis via Horn Encoding from synchronous Dataflow Programs. [Technical Report] RT-0492, Université Lyon 1 Claude Bernard, LIP & INSA, CITI 2017, pp.25. 〈hal-01614637〉
  • Christophe Alias. Improving Communication Patterns in Polyhedral Process Networks. [Research Report] RR-9131, INRIA Grenoble – Rhône-Alpes. 2017, pp.1-13. 〈hal-01665155〉
  • Romain Fontaine, Lionel Morel, Laure Gonnord. Combining dataflow programming and polyhedral optimization, a case study. [Technical Report] RT-0490, Inria Rhône-Alpes; CITI – CITI Centre of Innovation in Telecommunications and Integration of services; LIP – ENS Lyon. 2017, pp.40. 〈hal-01572439〉
  • Laure Gonnord, Szabolcs-Marton Bagoly, Lionel Morel. Static Analysis via Horn Encoding from synchronous Dataflow Programs. [Technical Report] RT-0492, Université Lyon 1 Claude Bernard, LIP & INSA, CITI 2017, pp.25. 〈hal-01614637〉
  • Christophe Alias, Fabrice Rastello, Alexandru Plesco. High-Level Synthesis of Pipelined FSM from Loop Nests. [Research Report] 8900, INRIA. 2016, pp.18. 〈hal-01301334v2〉
  • Maroua Maalej, Vitor Paisante, Fernando Magno Quintão Pereira, Laure Gonnord. Combining Range and Inequality Information for Pointer Disambiguation. [Research Report] RR-9076, ENS Lyon; CNRS; INRIA. 2016. 〈hal-01429777v2〉
  • Julien Braine, Laure Gonnord, David Monniaux. Verifying Programs with Arrays and Lists. [Intership report] ENS Lyon. 2016. 〈hal-01337140〉
  • Maroua Maalej, Laure Gonnord. Do we still need new Alias Analyses?. [Research Report] RR-8812, Université Lyon Claude Bernard / Laboratoire d’Informatique du Parallélisme. 2015. 〈hal-01228581〉
  • Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, Yun Zou. Mono-parametric Tiling is a Polyhedral Transformation. [Research Report] RR-8802, INRIA Grenoble – Rhône-Alpes; CNRS. 2015, pp.40. 〈hal-01219452〉
  • Christophe Alias, Alexandru Plesco. Data-aware Process Networks. [Rapport de recherche] RR-8735, Inria – Research Centre Grenoble – Rhône-Alpes; INRIA. 2015, pp.32. 〈hal-01158726〉
  • Laure Gonnord, Peter Schrammel. Abstract Acceleration in Linear relation analysis (extended version). 2013. 〈hal-00787212〉
  • Paul Feautrier, Abdoulaye Gamatié, Laure Gonnord. Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction. 2013. 〈hal-00780521v2〉
  • Guillaume Andrieu, Christophe Alias, Laure Gonnord. Modular termination of C programs. [Research Report] RR-8166, INRIA. 2012. 〈hal-00760917v2〉
  • Christophe Alias, Bogdan Pasca, Alexandru Plesco. FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores. [Research Report] RR-7674, INRIA. 2011, pp.33. 〈inria-00606977〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis. [Research Report] RR-7648, INRIA. 2011, pp.16. 〈inria-00601822〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Kernel Offloading with Optimized Remote Accesses. [Research Report] RR-7697, INRIA. 2011, pp.29. 〈inria-00611179〉
  • Vlad Rusu, Laure Gonnord, Benoît Combemale. Formally Tracing Executions From an Analysis Tool Back to a Domain Specific Modeling Language’s Operational Semantics. [Research Report] RR-7423, INRIA. 2010. 〈inria-00526561〉
  • Laure Gonnord, Nicolas Halbwachs. Abstract acceleration in Linear relation analysis. 2010. 〈hal-00785116〉
  • Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.. [Research Report] RR-7281, INRIA. 2010, pp.19. 〈inria-00482035〉
  • Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord. Bounding the Computational Complexity of Flowchart Programs with Multi-dimensional Rankings. [Research Report] RR-7235, INRIA. 2010, pp.32. 〈inria-00464356〉
  • Loïc Besnard, Thierry Gautier, Matthieu Moy, Jean-Pierre Talpin, Kenneth Johnson, et al.. Automatic translation of C/C++ parallel code into synchronous formalism using an SSA intermediate form. [Research Report] RR-6976, INRIA. 2009, pp.16. 〈inria-00400272〉
  • Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord, Clément Quinson. Program Termination and Worst Time Complexity with Multi-Dimensional Affine Ranking Functions. [Research Report] 2009, pp.31. 〈inria-00434037〉
  • Laure Gonnord, Jean-Philippe Babau. Resource Properties Expression and Runtime assurance for embedded programs, using Qinna, a component-based software architecture. [Research Report] RR-6565, INRIA. 2008. 〈inria-00289937v2〉
  • Laure Gonnord, Jean-Philippe Babau. Resource management with Qinna framework : the remote viewer case study. [Technical Report] RR-6562, INRIA. 2008. 〈inria-00288593v2〉

 

Habilitation à diriger des recherches2 documents

  • Laure Gonnord. Contributions to program analysis: expressivity and scalability. Computation and Language [cs.CL]. Université Lyon 1 Claude Bernard, 2017. 〈tel-01633065v2〉
  • Matthieu Moy. Modélisation à haut niveau d’abstraction pour les systèmes embarqués. Systèmes embarqués. Université de Grenoble, 2014. 〈tel-01054555〉