The CASH team was created at LIP laboratory on January 1st 2018 as an Inria “Équipe Projet Commune on June 1st 2019.”
The advent of parallelism in supercomputers and in more classical end-user computers increases the need for high-level code optimization and improved compilers. The need for power-efficient computing have motivated the raise of various kinds of accelerators like GPU and more recently many-cores and FPGA in data-center. Writing efficient applications for these heterogeneous systems requires new approaches for software, compilers and runtimes.
Parallelism based on dataflow is one way to address this issue. A dataflow application is made of several actors that can perform computations and communicate with other actors. It can be implemented in several ways: as software running on a parallel general-purpose architecture or on accelerators like GPU or many-core, or as hardware implementation, possibly running on reconfigurable chips (FPGA).
The overall objective of the CASH team is to take advantage of the characteristics of the specific hardware (generic hardware, hardware accelerators or FPGA) to compile energy efficient software and hardware. The long-term objective is to provide solutions for the end-user developers to use at their best the huge opportunities of these emerging platforms.
The research directions of the team are:
- Parallel and Dataflow Programming Models. We believe the dataflow paradigm is a good fit to allow safe and efficient ways to program on parallel architecture.
- Expressive, Scalable and Certified Static Analyses. We work on improving the precision and the scalability of static analysis approaches, as well as their reliability using proof assistant to prove their correctness.
- Optimizing Program Transformations. We study both heavyweight optimizations like polyhedral transformations and fast optimizations that are efficient enough to allow global analysis of large-scale programs. Our work is applied both to compilation of software and high-level synthesis.
- Simulation and Hardware. We study simulation of hardware in different context like systems-on-a-chip and supercomputers.
For more information, please contact the team leader: Matthieu Moy.