CASH

• Dataflow representations of parallel programs

  Dataflow models are a natural intermediate representation for hardware compilers (HLS) and more generally for parallelizing compilers. A dataflow model is a partition of the computation into processes and a partition of the flow dependences into channels. This partitioning prepares resource allocation and medium-grain communications.

• Expressivity and Scalability of Static Analyses

  We design expressive and scalable static analyses for compilers. The analyses we design are mainly driven by the HPC dataflow optimizations; however we will also target other kinds of analyses applicable to more general purpose programs.

• Compilation and Scheduling of Dataflow Programs
  

  Relying extensively on the polyhedral model, we propose to design  compiler analyses and optimizations for a medium-grain dataflow model. We also exploit these techniques to improve the compilation of dataflow languages based on actors. The polyhedral model was originally designed to analyze imperative programs and must be redefined in light of dataflow semantics.

• Efficient HLS-specific Dataflow Optimizations
  

  High-level synthesis (HLS) consists in compiling a kernel into a circuit. We design front-end level compiler algorithms to produce HPC hardware accelerators with the right resource usage (parallelism, data transfers).

• Simulation of Hardware
  

  We simulate systems written in the loosely timed coding style where the timing of the platform is not modeled precisely, and which allows the fastest simulations. We also work on the simulation of the data-aware process networks intermediate representation.

Main collaborations: XtremLogic, STMicroElectronics, Kalray, and several academic compiler teams (Colorado State Univ (US), Univ of Mineas Gerais (Brasil)