Ph.D Proposals:
- Starting September 2021
High Performance Code Generation for Abstract Data Types
Gabriel Radanne and Laure Gonnord
Internship proposals:
Master 2 Recherche:
- As part of the POLYTRACE Inria exploratory action, Christophe Alias with Keiji Kimura (Japan) – High-Performance Compilation Schemes using Dynamic Analysis
- As part of the HLSIMU projet Emergence ENS, Christophe Alias, with Matthieu Moy – Stratégies de compilation pour la synthèse de circuits
- [2021-2022] Yannick Zakowski and Gabriel Radanne – CFG Patterns: A new tool to formally verify optimisations in Vellvm
- [2021-2022] Gabriel Radanne and Florian Angeletti – Good error messages and documentation for OCaml modules via diffing
- [2021-2022] Gabriel Radanne and Laure Gonnord – Type indexing in OCaml: search and find functions in a large ecosystem
- [update 2020-21]: Yannick Zakowski with Ludovic Henrio – A parameterized bisimulation for interaction trees
- [update 2020-21]: Ludovic Henrio with Rabéan Ameur Boulifa and Eric Madelaine – Refinement for open automata
- [update 2020-21]: As part of the CAPESA Project, LG/MM/LH with Sebastien Mosser (Montreal) rewritingCode and Study Docker with compilation techniques
- [update 2020-21] LG with C. Collange (Inria Rennes): Static analysis for GPUs
- [update 2020-21] LG/YZ : Static Analysis in the certified SSA-compiler VELLVM.
- [update 2020-21]: As part of the CODAS Project LG with C. Fuhs (London) Scheduling data-structures with term rewriting techniques.
- Dataflow explicit futures: Formalisation and/or experimentation
- Dynamic Allocation in Embedded Systems with Several Memory Types (in collaboration with CITI lab)
- Code Generation for Simulation of Parallel Process Networks
- Scalability of the interference analysis for a multi-core platform
- Interference analysis for the new Kalray MPPA3 many-core
- Programming models for optimised compilation (pdf)
- Hardware Compilation: Recover the FIFOs!
- Ordonnancement de processus sous contrainte de pipeline
- Hierarchical Parallelization (version française :Parallélisation Hiérarchique)
- Analyse de WCET pour réseaux de processus
Master 1:
- Dataflow explicit futures: Formalisation and/or experimentation
- Simulation et outils de debug pour réseaux de processus
- [update 2020-21] POM (Lyon 1) with LG : frontend pour des analyses statiques, et outils pour l’édition numérique
Old proposals (already taken):
- In partnership with the Aniah startup :
- Theoretical complexity of graph-analysis for electrical circuit error detection
- Formulation généralisée de contraintes topologiques de circuits électriques
- Applying Symbolic Model-Checking Techniques to Circuit Electric Verification
- [2020-21] Matthieu Moy and Frédéric Suter – Workflow vs. Dataflow : Concepts, défis et simulation pour le calcul haute performance