Ph.D Proposals:
- [see Master 2 projects and contact us, we can propose Ph.D on the same topics]
Internship proposals:
Master 2 Recherche:
- In partnership with the Aniah startup : Complexité théorique d’un algorithme de vérification de cohérence de graphes représentant des circuits électriques and Formulation généralisée de contraintes topologiques de circuits électriques.
- As part of the POLYTRACE Inria exploratory action, Christophe Alias with Keiji Kimura (Japan) – High-Performance Compilation Schemes using Dynamic Analysis
- As part of the HLSIMU projet Emergence ENS, Christophe Alias, with Matthieu Moy – Stratégies de compilation pour la synthèse de circuits
- [2020-21] Matthieu Moy and Frédéric Suter – Workflow vs. Dataflow : Concepts, défis et simulation pour le calcul haute performance
- [update 2020-21]: Yannick Zakowski with Ludovic Henrio – A parameterized bisimulation for interaction trees
- [update 2020-21]: Ludovic Henrio with Rabéan Ameur Boulifa and Eric Madelaine – Refinement for open automata
- [update 2020-21]: As part of the CAPESA Project, LG/MM/LH with Sebastien Mosser (Montreal) rewritingCode and Study Docker with compilation techniques
- [update 2020-21] LG with C. Collange (Inria Rennes): Static analysis for GPUs
- [update 2020-21] LG/YZ : Static Analysis in the certified SSA-compiler VELVM.
- [update 2020-21]: As part of the CODAS Project LG with C. Fuhs (London) Scheduling data-structures with term rewriting techniques.
- Dataflow explicit futures: Formalisation and/or experimentation
- Dynamic Allocation in Embedded Systems with Several Memory Types (in collaboration with CITI lab)
- Code Generation for Simulation of Parallel Process Networks
- Scalability of the interference analysis for a multi-core platform
- Interference analysis for the new Kalray MPPA3 many-core
- Programming models for optimised compilation (pdf)
- Hardware Compilation: Recover the FIFOs!
- Ordonnancement de processus sous contrainte de pipeline
- Hierarchical Parallelization (version française :Parallélisation Hiérarchique)
- Analyse de WCET pour réseaux de processus
- Searching in libraries by types
Master 1:
- Dataflow explicit futures: Formalisation and/or experimentation
- Simulation et outils de debug pour réseaux de processus
- [update 2020-21] POM (Lyon 1) with LG : frontend pour des analyses statiques, et outils pour l’édition numérique